UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 1028

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

1026
Setting of HALT mode
Notes 1. Non-maskable interrupt request signal (INTWDT) or unmasked maskable interrupt request signal
2. RESET pin input, reset signal (WDTRES) generation by watchdog timer overflow, reset signal
3. Unmasked external interrupt request signal (INTP00, INTP01, INTP02 to INTP07 (V850E/IG3 only),
4. RESET pin input, reset signal (LVIRES) generation by low-voltage detector (LVI), or reset signal
5. Unmasked external interrupt request signal (INTP00, INTP01, INTP02 to INTP07 (V850E/IG3 only),
6. Oscillation stabilization time count by oscillation stabilization time wait control (OST)
7. Oscillation stabilization time count by oscillation stabilization time wait control (OST)
Interrupt request
(LVIRES) generation by low-voltage detector (LVI), or reset signal (POCRES) generation by power-
on-clear circuit (POC)
INTP08 to INTP13, INTP17, INTP18, INTADT0, or INTADT1) or unmasked internal interrupt request
signal from (CSIB-related interrupt request signal in the slave mode) peripheral functions operable in
STOP mode
(POCRES) generation by power-on-clear circuit (POC)
INTP08 to INTP13, INTP17, INTP18, INTADT0, or INTADT1) or unmasked internal interrupt request
signal (CSIB-related interrupt request signal in the slave mode) from peripheral functions operable in
IDLE mode
The oscillation stabilization time is necessary after release of reset because the PLL is initialized by a
reset. The stabilization time is the time determined by default.
The stabilization time is determined by the setting of the OSTS register.
HALT mode
Wait for stabilization of
(oscillation) and PLL
System reset
Note 1
Note 6
Setting of STOP mode
Note 2
CHAPTER 21 STANDBY FUNCTION
Figure 21-1. Status Transition
User’s Manual U18279EJ3V0UD
Interrupt request
Normal operation mode
Wait for stabilization of
oscillation and PLL
Note 7
STOP mode
System reset
Note 6
Note 3
Note 4
Setting of IDLE mode
Interrupt request
IDLE mode
Wait for stabilization of
(oscillation) and PLL
System reset
Note 5
Note 6
Note 4