UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 300

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

298
(2) TABn control register 1 (TABnCTL1)
Note The 6-phase PWM output mode cannot be used when only TABn is used. For details, see CHAPTER 10
Cautions 1. The TABnEST bit is valid only in the external trigger pulse output mode or one-shot pulse
The TABnCTL1 register is an 8-bit register that controls the operation of TABn.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
MOTOR CONTROL FUNCTION.
2. External event count input is selected in the external event count mode regardless of the
3. Set the TABnEEE and TABnMD2 to TABnMD0 bits when the TABnCTL0.TABnCE bit = 0.
4. Be sure to set bits 3, 4, and 7 to “0”.
TABnCTL1
output mode. In any other mode, writing 1 to this bit is ignored.
value of the TABnEEE bit.
(The same value can be written when the TABnCE bit = 1.) The operation is not guaranteed
when rewriting is performed with the TABnCE bit = 1.
performed, clear the TABnCE bit to 0 and then set the bits again.
(n = 0, 1)
After reset: 00H
TABnEEE
TABnEST
TABnMD2
The TABnEEE bit selects whether counting is performed with the internal count clock
or the valid edge of the external event count input.
Read value of the TABnEST bit is always 0.
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB)
0
1
0
1
0
0
0
0
0
1
1
1
1
7
TABnEST TABnEEE
TABnMD1
Disable operation with external event count input (EVTBn pin).
(Perform counting with the count clock selected by the
TABnCTL0.TABnCKS0 to TABnCKS2 bits.)
Generate a valid signal for external trigger input.
• In one-shot pulse output mode:
• In external trigger pulse output mode:
Enable operation with external event count input (EVTBn pin).
(Perform counting at the valid edge of the external event count input
signal (EVTBn pin).)
R/W
A one-shot pulse is output with writing 1 to the TABnEST bit as the trigger.
A PWM waveform is output with writing 1 to the TABnEST bit as the trigger.
6
0
0
1
1
0
0
1
1
Address: TAB0CTL1 FFFFF5E1H, TAB1CTL1 FFFFF621H
User’s Manual U18279EJ3V0UD
TABnMD0
5
0
1
0
1
0
1
0
1
Interval timer mode
External event count mode
External trigger pulse output mode
One-shot pulse output mode
PWM output mode
Free-running timer mode
Pulse width measurement mode
6-phase PWM output mode
4
0
Software trigger control
Count clock selection
3
0
−
Timer mode selection
TABnMD2 TABnMD1 TABnMD0
2
Note
If rewriting was mistakenly
1
0