UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 881

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.6.6 Wait state
receive data (i.e., is in a wait state).
canceled for both the master and slave devices, the next data transfer can begin.
The wait state is used to notify the communication partner that a device (master or slave) is preparing to transmit or
Setting the SCL pin to low level notifies the communication partner of the wait status. When wait status has been
Transfer lines
(a) When master device has a nine-clock wait and slave device has an eight-clock wait
Master
Slave
ACKE0
SDA
SCL
SCL
SCL
IIC0
IIC0
(master: transmission, slave: reception, and IICC0.ACKE0 bit = 1)
H
D2
6
6
D1
Figure 17-11. Wait State (1/2)
7
7
Master returns to high
impedance but slave
is in wait state (low level).
Wait after output
of eighth clock.
User’s Manual U18279EJ3V0UD
CHAPTER 17 I
D0
8
8
Wait state
from slave
9
ACK
2
C BUS
9
FFH is written to IIC0 register or
IICC0.WREL0 bit is set to 1.
Wait after output
of ninth clock.
Wait state
from master
IIC0 data write (cancel wait)
D7
1
1
D6
2
2
D5
3
3
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