UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 773

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.6 Control Modes
(1) Single mode/FIFO mode
The single mode or FIFO mode can be selected by using the UBFIC0.UBMOD bit.
(a) Single mode
(b) FIFO mode
• Each of the UBRX and UBTX registers consists of 8 bits × 1 stage.
• When 1 byte of data is received, the INTUBTIR signal is generated.
• If the next reception operation of UARTB is ended before the receive data of the UBRX register is read
• Receive FIFO (UBRXAP register) consists of 16 bits × 16 stages and transmit FIFO consists of 8 bits ×
• Receive FIFO can recognize error data by reading the 16-bit UBRXAP register only when a reception
• Transmission is started when transmission is enabled (UBCTL0.UBTXE bit = 1) after transmit data of
• The pending mode or pointer mode can be selected for the generation timing of the INTUBTIT and
after the INTUBTIR signal has been generated, the INTUBTIRE signal is generated and an overrun
error occurs.
16 stages.
error (parity error or framing error) occurs.
at least the number set as the trigger by the UBFIC2.UBTT3 to UBFIC2.UBTT0 bits and 16 bytes or
less are written to transmit FIFO.
INTUBTIR signals.
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE B (UARTB)
User’s Manual U18279EJ3V0UD
771