UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 1116

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(5) I
(T
V
Notes 1. The first clock pulse is generated after a hold time during the start condition.
1114
SCL clock frequency
Bus free time (between stop condition
and start condition)
Hold time
SCL clock low-level width
SCL clock high-level width
Start/restart condition setup time
Data hold time
Data setup time
SDA, SCL signal rise time
SDA, SCL signal fall time
Stop condition setup time
Pulse width of spike suppressed by
input filter
Each bus line capacitive load
SS0
A
= −40 to +85°C, V
2
= V
C bus timing
2. The system must internally supply a hold time of at least 300 ns for the SDA signal (at V
3. If the system does not extend the low hold time (t
4. The high-speed mode I
5. Cb: Total capacitance of one bus line (unit: pF)
SS1
Note 1
to fill the undefined area at the falling edge of SCL.
(t
that the following conditions are satisfied.
• If system does not extend the low status hold time of the SCL signal
• If system extends the low status hold time of SCL signal
= EV
HD:DAT
Parameter
t
Sends the next data bit to the SDA line before the SCL line is released (t
1250 ns: standard mode I
SU: DAT
) must be satisfied.
SS0
CBUS-compatible
master
I
2
C mode
≥ 250 ns
= EV
DD0
SS1
= V
= AV
DD1
= EV
SS0
2
C bus can be used in the standard mode I
CHAPTER 28 ELECTRICAL SPECIFICATIONS
f
t
t
t
t
t
t
t
t
t
t
Cb
t
= AV
CLK
BUF
HD:STA
LOW
HIGH
SU:STA
HD:DAT
SU:DAT
R
F
SU:STO
SP
DD0
2
C bus specification).
Symbol
= EV
SS1
= AV
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User’s Manual U18279EJ3V0UD
DD1
−
−
= AV
SS2
= 0 V, C
DD0
MIN.
0
250
4.7
4.0
4.7
4.0
4.7
5.0
4.0
Note 2
0
−
−
−
−
Standard Mode
= AV
L
LOW
DD1
= 50 pF)
) of the SCL signal, the maximum data hold time
= AV
MAX.
1000
100
300
400
−
−
−
−
−
−
−
−
−
−
DD2
= 4.0 to 5.5 V,
2
C bus system. In this case, make sure
20 + 0.1Cb
20 + 0.1Cb
100
MIN.
0
1.3
0.6
1.3
0.6
0.6
0.6
High-Speed Mode
Note 2
0
−
0
−
Note 4
Rmax
Note 5
Note 5
. + t
SU:DAT
0.9
IHmin
MAX.
400
300
300
400
50
−
−
−
−
−
−
−
−
Note 3
= 1000 + 250 =
. of SCL signal)
Unit
kHz
μ
μ
μ
μ
μ
μ
μ
ns
ns
μ
ns
pF
ns
s
s
s
s
s
s
s
s