UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 984

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.13 DMA Transfer End
the interrupt controller (INTC) (n = 0 to 3).
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(4) DMA start factors
(5) Program execution and DMA transfer with internal RAM
(6) Timing of setting DCHCn.TCn bit
(7) Read values of DSAn and DDAn registers
(8) CLR1, NOT1, and SET1 instructions
When DMA transfer ends and the DCHCn.TCn bit is set to 1, a DMA transfer end interrupt (INTDMAn) is issued to
Note with caution when setting two or more DMA channels with the same factor.
If two or more DMA channels are started with the same factor, the DMA channel with a lower priority may be
acknowledged before the DMA channel with a higher priority.
Do not execute DMA transfer to/from the internal RAM and an instruction in the internal RAM simultaneously.
The DCHCn.TCn bit is usually set to 1 at the end of DMA transfer. In the case of DMA transfer that is initiated
from the internal RAM, however, it is set 4 clocks after end of the last transfer (n = 0 to 3).
If the values of the DSAn and DDAn registers are read during DMA transfer, values in the middle of being
updated may be read (n = 0 to 3).
For example, if the DSAnH register and the DSAnL register are read in that order when the value of the DMA
transfer source address (DSAn register) is “0000FFFFH” and the counting direction is incremental (when the
SADn1 and SADn0 bits of the DADCn register = 00), the value of the DSAnL register differs as follows
depending on whether DMA transfer is executed immediately after the DSAnH register has been read.
(a) If DMA transfer does not occur while the DSAn register is being read
(b) If DMA transfer occurs while the DSAn register is being read
Write the CLR1, NOT1, and SET1 instructions after reading a register and then manipulating the target bit. To
set the DCHCn.Enn bit to 1 by using the SET1 instruction, therefore, the TCn bit is cleared to 0 when the
DCHCn.TCn bit = 1 (n = 0 to 3).
<1> Reading DSAnH register: DSAnH = 0000H
<2> Reading DSAnL register: DSAnL = FFFFH
<1> Reading DSAnH register: DSAnH = 0000H
<2> Occurrence of DMA transfer
<3> Incrementing DSAn register: DSAn = 00010000H
<4> Reading DSAnL register: DSAnL = 0000H
CHAPTER 19 DMA FUNCTIONS (DMA CONTROLLER)
User’s Manual U18279EJ3V0UD