UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 967

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.3.3 DMA transfer count registers 0 to 3 (DBC0 to DBC3)
These registers store the remaining transfer count during DMA transfer.
register, a new DMA byte transfer count for DMA transfer can be specified during DMA transfer (see 19.8 Next
Address Setting Function). When setting the next address, the newly set value of the DBCn register is transferred
to the slave register and becomes valid only when DMA transfer has been completed normally and the DCHCn.TCn
bit is set to 1, or when the DCHCn.INITn bit is set to 1 (n = 0 to 3). However, the set value of the DBCn register is
invalid even when the DCHCn.Enn bit is cleared to 0 to disable DMA transfer and then the DBCn register is set.
The DBC0 to DBC3 registers are 16-bit registers that set the byte transfer count for DMA channel n (n = 0 to 3).
Since these registers are configured as 2-stage FIFO buffer registers consisting of the master register and slave
These registers are decremented by 1 for each transfer, and transfer ends when a borrow occurs.
These registers can be read or written in 16-bit units.
Reset makes these registers undefined.
Caution Do not set the DBCn register while DMA is suspended.
Remark
If the DBCn register is read during DMA transfer after a terminal count has occurred without the register
being overwritten, the value set immediately before the DMA transfer will be read out (0000H will not be
read, even if DMA transfer has ended).
(n = 0 to 3)
After reset:
DBCn
BCn15 to BCn0
FFFFH
0000H
0001H
BCn15
Undefined
BCn7
15
7
:
CHAPTER 19 DMA FUNCTIONS (DMA CONTROLLER)
Transfer count 1 or remaining transfer count
Transfer count 2 or remaining transfer count
Transfer count 65536 (2
Transfer count setting (store remaining transfer count during DMA transfer)
BCn14
BCn6
14
6
R/W
User’s Manual U18279EJ3V0UD
BCn13
BCn5
13
Address: DBC0 FFFFF0C0H, DBC1 FFFFF0C2H,
5
BCn12
BCn4
16
12
DBC2 FFFFF0C4H, DBC3 FFFFF0C6H
4
) or remaining transfer count
BCn11
BCn3
11
3
:
BCn10
BCn2
10
2
BCn9
BCn1
9
1
BCn8
BCn0
8
0
965