UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 863

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note This flag’s signal is invalid when the IICE0 bit = 0.
WREL0
WTIM0
ACKE0
Condition for clearing (WREL0 bit = 0)
• Automatically cleared after execution
• Reset
Condition for clearing (SPIE0 bit = 0)
• Cleared by instruction
• Reset
An interrupt is generated at the falling of the 9th clock during address transfer independently of the setting of this bit.
The setting of this bit is valid when the address transfer is completed. When in master mode, a wait is inserted at the
falling edge of the ninth clock during address transfers. For a slave device that has received a local address, a wait is
inserted at the falling edge of the ninth clock after ACK is issued. However, when the slave device has received an
extension code, a wait is inserted at the falling edge of the eighth clock.
Condition for clearing (WTIM0 bit = 0)
• Cleared by instruction
• Reset
The ACKE0 bit setting is invalid for address reception. In this case, ACK is generated when the addresses match.
However, the ACKE0 bit setting is valid for address reception of the extension code.
Condition for clearing (ACKE0 bit = 0)
• Cleared by instruction
• Reset
SPIE0
0
1
0
1
0
1
0
1
Note
Note
Note
Note
Disable
Enable
Interrupt request is generated at the eighth clock’s falling edge.
Master mode: After output of eight clocks, clock output is set to low level and wait is set.
Slave mode: After input of eight clocks, the clock is set to low level and wait is set for master device.
Interrupt request is generated at the ninth clock’s falling edge.
Master mode: After output of nine clocks, clock output is set to low level and wait is set.
Slave mode: After input of nine clocks, the clock is set to low level and wait is set for master device.
Disable acknowledgment.
Enable acknowledgment. During the ninth clock period, the SDA line is set to low level.
Do not cancel wait
Cancel wait. This setting is automatically cleared to 0 after wait is canceled.
Enable/disable generation of interrupt request when stop condition is detected
Control of wait and interrupt request generation
User’s Manual U18279EJ3V0UD
CHAPTER 17 I
Wait cancellation control
Acknowledgment control
Condition for setting (WREL0 bit = 1)
• Set by instruction
Condition for setting (SPIE0 bit = 1)
• Set by instruction
Condition for setting (WTIM0 bit = 1)
• Set by instruction
Condition for setting (ACKE0 bit = 1)
• Set by instruction
2
C BUS
(2/4)
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