UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 230

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

228
(c) Notes on rewriting TAAnCCR0 register
If the value of the TAAnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter
may overflow. When an overflow may occur, stop counting and then change the set value.
Remarks 1. Interval time (1):
If the value of the TAAnCCR0 register is changed from D
less than D
has been rewritten. Consequently, the value of the 16-bit counter that is compared is D
Because the count value has already exceeded D
overflows, and then counts up again from 0000H. When the count value matches D
signal is generated and the output of the TOAm0 pin is inverted.
Therefore, the INTTAnCC0 signal may not be generated at the interval time “(D
or “(D
+ 1) × Count clock cycle”.
TAAnCCR0 register
2
INTTAnCC0 signal
TOAm0 pin output
+ 1) × Count clock cycle” originally expected, but may be generated at an interval of “(10000H + D
16-bit counter
TAAmOL0 bit
2. V850E/IF3: n = 0 to 4, m = 2, 4
1
TAAnCE bit
, the count value is transferred to the CCR0 buffer register as soon as the TAAnCCR0 register
Interval time (NG): (10000H + D
Interval time (2):
V850E/IG3: n = 0 to 4, m = 2 to 4
FFFFH
0000H
CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA)
L
Interval time (1)
(D
(D
User’s Manual U18279EJ3V0UD
1
2
+ 1) × Count clock cycle
+ 1) × Count clock cycle
D
1
D
1
2
+ 1) × Count clock cycle
D
2
Interval time (NG)
2
, however, the 16-bit counter counts up to FFFFH,
D
1
1
to D
2
while the count value is greater than D
D
2
D
2
Interval
time (2)
D
2
1
+ 1) × Count clock cycle”
2
.
2
, the INTTAnCC0
2
but
2