UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 948

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

18.7 Idle State Insertion Function
946
The idle state is inserted after a read cycle or a write cycle to the SRAM, external ROM, or external I/O.
(1) Bus cycle control register (BCC)
To facilitate interfacing with low-speed devices, an idle state (TI) can be inserted into the current bus cycle
after the T2 state (after TW state if a data wait state is inserted) to secure the data output float delay time on
memory read access for each CS space. The bus cycle following the T2 state (or TW state) starts after the
idle state is inserted.
An idle state can be inserted after a write access by using the bus clock division control register (DVC).
The idle state insertion setting can be specified by program using the BCC register. Immediately after the
system reset, idle state insertion is automatically programmed for all memory blocks. For the timing when an
idle state is inserted, see 18.8 Bus Timing.
This register can be read or written in 16-bit units.
Reset sets this register to AAAAH.
Cautions 1. The internal ROM, internal RAM, and on-chip peripheral I/O areas are not subject to idle
Caution Be sure to set bits 0, 2, 4, 6, 8, 10, 12, and 14 to “0”, and set bits 5, 7, 9, 11, 13, and 15 to
CSn signal
CSn signal
After reset: AAAAH
2. Write to the BCC register after reset, and then do not change the set values. Also, when
3. The chip select signal (CSn) does not become active in the idle state (n = 0, 1).
“1”. If they are set other than above, the operation is not guaranteed.
BCC
state insertion.
changing the initial values of the BCC register, do not access an external memory area
until the settings are complete. However, it is possible to access external memory
areas whose initialization settings are complete.
Insertion of an idle state can be specified for each CSn space after completion of a
read cycle or a write cycle.
If the DVC.BCWI bit = 0, however, the idle state is inserted only after completion of a
read cycle and not after completion of a write cycle.
BCn1
15
1
1
7
0
1
Not inserted
Inserted
CHAPTER 18 BUS CONTROL FUNCTION
R/W Address: FFFFF48AH
14
0
6
0
Specification of idle state inserted in each CSn space (n = 0, 1)
User’s Manual U18279EJ3V0UD
13
1
1
5
12
0
4
0
BC11
CS1
11
1
3
10
0
2
0
BC01
CS0
9
1
1
0
0
8
0