UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 774

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

772
(2) Pending mode/pointer mode
The pending mode or pointer mode can be selected by using the UBFIC0.UBITM and UBFIC0.UBIRM bits in
the FIFO mode (UBFIC0.UBMOD bit = 1).
If transmission is started by writing data of more than double the amount set as the trigger by the
UBFIC2.UBTT3 to UBFIC2.UBTT0 bits to transmit FIFO, the transmission enable interrupt request signal
(INTUBTIT) may occur more than once. The reception end interrupt request signal (INTUBTIR) may also
occur more than once if the number of receive data set as the trigger by the UBFIC2.UBRT3 to
UBFIC2.UBRT0 bits is 8 bytes or less in receive FIFO. In the pending or pointer mode, it can be specified
how an interrupt is handled after it has been held pending.
(a) Pending mode
(i) During transmission (writing to transmit FIFO)
• If the data of the first transmission enable interrupt request signal (INTUBTIT) is not written to
• In the pending mode, transmit data of the number set as the trigger by the UBFIC2.UBTT3 to
• Fix the UBFIC2.UBTT3 to UBFIC2.UBTT0 bits to 0000 (set number of transmit data: 1 byte) to
transmit FIFO after the interrupt has occurred, the second INTUBTIT signal does not occur (is held
pending) even if the generation condition of the second INTUBTIT signal is satisfied (when
transmit data of the number set as the trigger by the UBFIC2.UBTT3 to UBFIC2.UBTT0 bits is
transferred from transmit FIFO to the transmit shift register).
When data for the first INTUBTIT signal is later written to transmit FIFO, the pending INTUBTIT
signal is generated
Note The number of pending interrupts is as follows.
UBFIC2.UBTT0 bits is always written to transmit FIFO when the transmission enable interrupt
request signal (INTUBTIT) occurs. Writing data to transmit FIFO is prohibited if the data is more or
less than the specified number. If data more or less than the specified number is written, the
operation is not guaranteed.
write transmit data to transmit FIFO by DMA. If any other setting is made, the operation is not
guaranteed.
When trigger is set to 1 byte (UBFIC2.UBTT3 to UBFIC2.UBTT0 bits = 0000): 15 times max.
When trigger is set to 2 bytes (UBFIC2.UBTT3 to UBFIC2.UBTT0 bits = 0001): 7 times max.
When trigger is set to 6 bytes (UBFIC2.UBTT3 to UBFIC2.UBTT0 bits = 0101): 1 time max.
When trigger is set to 7 bytes (UBFIC2.UBTT3 to UBFIC2.UBTT0 bits = 0110): 1 time max.
When trigger is set to 8 bytes (UBFIC2.UBTT3 to UBFIC2.UBTT0 bits = 0111): 1 time max.
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE B (UARTB)
Note
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User’s Manual U18279EJ3V0UD
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