UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 864

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

862
Remark The STT0 bit is 0 if it is read after data setting.
Cautions concerning set timing
For master reception:
For master transmission: A start condition may not be generated normally during the ACK period. Set to 1 during the
• Cannot be set to 1 at the same time as the SPT0 bit.
• When the STT0 bit is set to 1, setting the STT0 bit to 1 again is disabled until the setting is cleared to 0.
Condition for clearing (STT0 bit = 0)
• When the STT0 bit is set to 1 in the communication
• Cleared by loss in arbitration
• Cleared when start condition is generated by master
• When the LREL0 bit = 1 (exit from communications)
• When the IICE0 bit = 0 (operation stop)
• Reset
reservation disabled status
device
STT0
0
1
Do not generate a start condition.
When bus is released (in STOP mode):
When a third party is communicating
In the wait state (when master device):
Generate a start condition (for starting as master). The SDA line is changed from high level to low level
Generates a restart condition after releasing the wait.
while the SCL line is high level and then the start condition is generated. Next, after the rated amount of
time has elapsed, the SCL line is changed to low level (wait status).
• When communication reservation function is enabled (IICF0.IICRSV0 bit = 0)
• When communication reservation function is disabled (IICRSV0 bit = 1)
Functions as the start condition reservation flag. When set to 1, automatically generates a start
condition after the bus is released.
The IICF0.STCF0 bit is set to 1 and the information set (1) to the STT0 bit is cleared. No start
condition is generated.
cleared to 0 and slave has been notified of final reception.
wait period that follows output of the ninth clock.
Cannot be set to 1 during transfer. Can be set to 1 only when the ACKE0 bit has been
User’s Manual U18279EJ3V0UD
CHAPTER 17 I
Start condition trigger
Condition for setting (STT0 bit = 1)
• Set by instruction
2
C BUS
(3/4)