UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 860

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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(8) Serial clock controller
(9) Serial clock wait controller
(10) ACK generator, stop condition detector, start condition detector, and ACK detector
(11) Data hold time correction circuit
(12) Start condition generator
(13) Stop condition generator
(14) Bus status detector
In master mode, this circuit generates the clock output via the SCL pin from a sampling clock.
This circuit controls the wait timing.
These circuits are used to generate and detect various statuses.
This circuit generates the hold time for data corresponding to the falling edge of the serial clock.
This circuit generates a start condition when the IICC0.STT0 bit is set.
However, in the communication reservation disabled status (IICF0.IICRSV0 bit = 1), when the bus is not
released (IICF0.IICBSY0 bit = 1), start condition requests are ignored and the IICF0.STCF0 bit is set to 1.
A stop condition is generated when the IIC0.SPT0 bit is set (1).
This circuit detects whether or not the bus is released by detecting start conditions and stop conditions.
However, as the bus status cannot be detected immediately following operation, the initial status is set by the
IICF0.STCEN0 bit.
User’s Manual U18279EJ3V0UD
CHAPTER 17 I
2
C BUS