UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 914

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
17.15
912
(1) When IICF0.STCEN0 bit = 0
(2) When IICF0.STCEN0 bit = 1
(3) When the IICC0.IICE0 bit of the V850E/IF3 and V850E/IG3 is set to 1 while communications with other devices
(4) Procedure for starting or stopping I
(5) After the IICC0.STT0 and IICC0.SPT0 bits have been set to 1, they must not be re-set without being cleared to
(6) If transmission has been reserved, set the IICC0.SPIE0 bit to 1 so that an interrupt request is generated by the
Immediately after I
regardless of the actual bus status. To execute master communication in the status where a stop condition
has not been detected, generate a stop condition and then release the bus before starting the master
communication.
Use the following sequence for generating a stop condition.
<1> Set the IICCL0 register.
<2> Set the IICC0.IICE0 bit.
<3> Set the IICC0.SPT0 bit.
Immediately after I
of the actual bus status. To generate the first start condition (IICC0.STT0 bit = 1), it is necessary to confirm
that the bus has been released, so as to not disturb other communications.
are in progress, the start condition may be detected depending on the status of the communication line. Be
sure to set the IICC0.IICE0 bit to 1 when the SCL and SDA lines are high level.
(a) Starting I
(b) Stopping I
0 first.
detection of a stop condition. After an interrupt request has been generated, the wait state will be released by
writing communication data to I
a stop condition, transmission will halt in the wait state because an interrupt request was not generated.
However, it is not necessary to set the SPIE0 bit to 1 for the software to detect the IICS0.MSTS0 bit.
Cautions
<1> Select the division clock by using the IICOCKS.IICOCKS1 and IICOCKS.IICOCKS0 bits and set the
<2> Specify the transfer speed by using the IICCL0 and IICX0 registers.
<3> Set the IICC0.IICE0 bit to 1 (to start I
When changing the transfer speed for I
<1> Clear the IICC0.IICE0 bit to 0 (to stop I
<2> Clear the IICOCKS.IICOCKSEN bit to 0 (to disable I
IICOCKS.IICOCKSEN bit to 1 (to enable I
2
C operation
2
C operation
2
2
C operation is enabled, the bus communication status (IICF0.IICBSY0 bit = 1) is recognized
C operation is enabled, the bus released status (IICBSY0 bit = 0) is recognized regardless
2
C, then transferring will begin. If an interrupt is not generated by the detection of
2
C operation
User’s Manual U18279EJ3V0UD
CHAPTER 17 I
2
C, do so after clearing the IICC0.IICE0 bit to 0.
2
C operation).
2
C operation).
2
C division clock operation).
2
C BUS
2
C division clock operation).