UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 247

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

the 16-bit counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform
from the TOAm1 pin. If the trigger is generated again while the counter is operating, the counter is cleared to 0000H
and restarted. (The output of the TOAm0 pin is inverted. The TOAm1 pin outputs a high-level regardless of the status
(high/low) when a trigger occurs.)
after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The
compare match interrupt request signal INTTAmCC1 is generated when the count value of the 16-bit counter matches
the value of the CCR1 buffer register.
bit counter matches the value of the CCRa buffer register and the 16-bit counter is cleared to 0000H.
is used as the trigger.
16-bit timer/event counter AA waits for a trigger when the TAAmCE bit is set to 1. When the trigger is generated,
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
The compare match interrupt request signal INTTAmCC0 is generated when the 16-bit counter counts next time
The value set to the TAAmCCRa register is transferred to the CCRa buffer register when the count value of the 16-
The valid edge of an external trigger input (TIAm0), or setting the software trigger (TAAmCTL1.TAAmEST bit) to 1
Remark
External trigger input
TAAmCCR0 register
TAAmCCR1 register
(only when software
INTTAmCC0 signal
INTTAmCC1 signal
TOAm0 pin output
TOAm1 pin output
Active level width = (Set value of TAAmCCR1 register) × Count clock cycle
Cycle = (Set value of TAAmCCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TAAmCCR1 register)/(Set value of TAAmCCR0 register + 1)
(TIAm0 pin input)
trigger is used)
16-bit counter
TAAmCE bit
V850E/IF3: m = 2, 4, a = 0, 1, V850E/IG3: m = 2 to 4, a = 0, 1
FFFFH
0000H
Figure 6-25. Basic Timing in External Trigger Pulse Output Mode
trigger
Wait
CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA)
for
Active level
width (D
Cycle (D
D
1
1
)
D
0
User’s Manual U18279EJ3V0UD
0
+ 1)
Active level
width (D
Cycle (D
D
1
1
)
D
0
0
+ 1)
D
D
0
1
D
1
D
0
Active level
width (D
Cycle (D
D
1
1
)
D
0
0
+ 1)
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