UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 602

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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(2) Tuning operation clearing procedure
(3) When not tuning TAAn
(4) Basic operation of TAAn during tuning operation
(e) Set the TAAnCE bit to 1 and set the TABnCE bit to 1 immediately after that to start the 6-phase PWM
To clear the tuning operation and exit the 6-phase PWM output mode, set the TAAn and TABn registers using
the following procedure.
<1> Clear the TABnCTL0.TABnCE bit to 0 and stop the timer operation.
<2> Clear the TAAnCTL0.TAAnCE bit to 0 so that TAAn can be separated.
<3> Stop the timer output by using the TABnIOC0 register.
<4> Clear the TAAnCTL1.TAAnSYE bit to 0 to clear the tuning operation.
Caution Manipulating (reading/writing) the other TABn, TAAn, and TMQn option registers is prohibited
When the match interrupt signal of TAAn is not necessary as the conversion trigger source that starts A/D
converters 0 and 1, TAAn can be used independently as a separate timer without being tuned. In this case, the
match interrupt signal of TAAn cannot be used as a trigger source to start A/D conversion in the 6-phase PWM
output mode.
TABnOPT3.TABnAT7 bits to 0.
The other control bits can be used in the same manner as when TAAn is tuned.
If TAAn is not tuned, the compare registers (TAAnCCR0 and TAAnCCR1) of TAAn are not affected by the
settings of the TABnOPT0.TABnCMS and TABnOPT2.TABnRDE bits. For the initialization procedure when
TAAn is not tuned, see (b) to (e) in 10.4.5 (1) Tuning operation starting procedure. (a) is not necessary
because it is a step used to set TAAn for the tuning operation.
The 16-bit counter of TAAn only counts up. The 16-bit counter is cleared by the set cycle value of the
TABnCCR0 register and starts counting from 0000H again. The count value of this counter is the same as the
value of the 16-bit counter of TAAn when it counts up. However, it is not the same when the 16-bit counter of
TABn counts down.
• When TABn counts up (same value)
• When TABn counts down (not same value)
16-bit counter of TABn: 0000H → M (up counting)
16-bit counter of TAAn: 0000H → M (up counting)
16-bit counter of TABn: M + 1 → 0001H (down counting)
16-bit counter of TAAn: 0000H → M (up counting)
output operation.
Rewriting the TABnCTL0, TABnCTL1, TABnIOC1, TABnIOC2, TAAnCTL0, and TAAnCTL1 registers is
prohibited during operation. The operation and the PWM output waveform are not guaranteed if any of
these registers is rewritten during operation. However, rewriting the TABnCTL0.TABnCE bit to clear it is
permitted. Manipulating (reading/writing) the other TABn, TAAn, and TMQn option registers is prohibited
until the TAAnCTL0.TAAnCE bit is set to 1 and then the TABnCE bit is set to 1.
until the TABnCE bit is set to 0 and then the TAAnCE bit is set to 0.
Therefore, fix the TABnOPT2.TABnAT2, TABnOPT2.TABnAT3, TABnOPT3.TABnAT6, and
CHAPTER 10 MOTOR CONTROL FUNCTION
User’s Manual U18279EJ3V0UD