UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 805

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UPD70F3451GC-UBT-A

Manufacturer Part Number
UPD70F3451GC-UBT-A
Description
MCU 32BIT 128KB FLASH 80LQFP
Manufacturer
Renesas Electronics America
Series
V850E/Ix3r
Datasheet

Specifications of UPD70F3451GC-UBT-A

Core Processor
RISC
Core Size
32-Bit
Speed
64MHz
Connectivity
CSI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
44
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Data Converters
A/D 10x12b, 4x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3451GC-UBT-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
(11) Example of reception error processing flow in FIFO mode (2)
Caution Reception can be continued by completing this control flow before reception of the next
data is ended. Extract the receive data and check if a reception error has occurred before
receive FIFO becomes empty. Note that this control flow is valid only when a parity error or
a framing error occurs.
(UBFIC0.UBRFC bit = 1).
If the next data is received before this control flow is ended, a reception error interrupt
request signal (INTUBTIRE) may occur even if the data has been received correctly.
Figure 15-22. Example of Reception Error Processing Flow in FIFO Mode (2)
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE B (UARTB)
Read UBRXAP register
Read UBSTR register
Read UBFIS0 register
Clear error flag
START
END
If an overflow error occurs, receive FIFO must be cleared
User’s Manual U18279EJ3V0UD
: Check error flag
: Check receive FIFO pointer
: Extract receive data and check error
803

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