UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 876

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.6 I
bus.
condition” generated via the I
ACK can be generated by either the master or slave device (normally, it is generated by the device that receives 8-bit
data).
level period can be extended and a wait can be inserted.
17.6.1 Start condition
start conditions for the SCL pin and SDA pin are generated when the master device starts a serial transfer to the slave
device. Start conditions can be detected when the device is used as a slave.
(IICS0.SPD0 bit = 1). When a start condition is detected, IICS0.STD0 bit is set to 1.
874
The following section describes the I
The master device generates the start condition, slave address, and stop condition.
The serial clock (SCL) is continuously output by the master device. However, in the slave device, the SCL’s low-
A start condition is met when the SCL pin is at high level and the SDA pin changes from high level to low level. The
A start condition is generated when the IICC0.STT0 bit is set to 1 after a stop condition has been detected
2
The transfer timing for the “start condition”, “address”, “transfer direction specification”, “data”, and “stop
C Bus Definitions and Control Methods
SDA
SCL
condition
Start
2
C bus’s serial data bus is shown below.
Address
Figure 17-5. I
1 to 7
SDA
SCL
2
C bus’s serial data communication format and the status generated by the I
R/W
8
Figure 17-6. Start Conditions
H
User’s Manual U18279EJ3V0UD
2
C Bus’s Serial Data Transfer Timing
ACK
CHAPTER 17 I
9
1 to 8
Data
2
C BUS
ACK
9
1 to 8
Data
ACK
9
condition
Stop
2
C