UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 68

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

66
(4) Program status word (PSW)
Remark
31 to 8
7
6
5
4
3
2
1
0
Bit position
PSW
The program status word (PSW) is a collection of flags that indicate the program status (instruction execution
result) and the CPU status.
When the contents of this register are changed using the LDSR instruction, the new contents become valid
immediately following completion of LDSR instruction execution. Interrupt request acknowledgment is held
pending while a write to the PSW is being executed by the LDSR instruction.
Bits 31 to 8 are reserved (fixed to 0) for future function expansion.
Note is explained on the following page.
31
RFU
NP
EP
ID
SAT
CY
OV
S
Z
Flag name
Note
Note
Note
Reserved field. Fixed to 0.
Indicates that non-maskable interrupt (NMI) servicing is in progress. This flag is set to 1 when
an NMI request is acknowledged, and disables multiple interrupts.
0: NMI servicing not in progress
1: NMI servicing in progress
Indicates that exception processing is in progress. This flag is set to 1 when an exception
occurs. Moreover, interrupt requests can be acknowledged even when this bit is set.
0: Exception processing not in progress
1: Exception processing in progress
Indicates whether maskable interrupt request acknowledgment is enabled.
0: Interrupt enabled (EI)
1: Interrupt disabled (DI)
Indicates that the result of executing a saturated operation instruction has overflowed and that
the calculation result is saturated. Since this is a cumulative flag, it is set to 1 when the result of
a saturated operation instruction becomes saturated, and it is not cleared to 0 even if the
operation results of successive instructions do not become saturated. This flag is neither set
nor cleared when arithmetic operation instructions are executed.
0: Not saturated
1: Saturated
Indicates whether carry or borrow occurred as the result of an operation.
0: No carry or borrow occurred
1: Carry or borrow occurred
Indicates whether overflow occurred during an operation.
0: No overflow occurred
1: Overflow occurred.
Indicates whether the result of an operation is negative.
0: Operation result is positive or 0.
1: Operation result is negative.
Indicates whether operation result is 0.
0: Operation result is not 0.
1: Operation result is 0.
RFU
CHAPTER 3 CPU FUNCTION
User’s Manual U18279EJ3V0UD
Description
8 7
NP
EP
6
ID
5
SAT
4
CY
3
OV
2
S Z
1
0
00000020H
After reset
(1/2)