UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 30

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

28
(2) Internal units
(a) CPU
(b) Bus control unit (BCU)
(c) ROM
(d) RAM
(e) Interrupt controller (INTC)
(f) Clock generator (CG)
The CPU uses five-stage pipeline control to enable single-clock execution of address calculations,
arithmetic logic operations, data transfers, and almost all other instruction processing.
Other dedicated on-chip hardware, such as a multiplier (32 bits × 32 bits → 64 bits) and a barrel shifter (32
bits), help accelerate complex processing.
The BCU controls the internal bus.
(i) DMA controller (DMAC)
This is flash memory that is mapped from address 00000000H.
During instruction fetch, ROM/flash memory can be accessed from the CPU in 1-clock cycles. The
internal ROM capacity and area differ as follows depending on the product.
The internal RAM capacity and area differ as follows depending on the product.
During instruction fetch or data access, data can be accessed from the CPU in 1-clock cycles.
This controller handles hardware interrupt requests (INTP00, INTP01, INTP08 to INTP18, INTADT0,
INTADT1) from on-chip peripheral hardware and external hardware. Eight levels of interrupt priorities can
be specified for these interrupt requests, and multiple-interrupt servicing control can be performed.
The clock generator includes two basic operation modes: PLL mode (fixed to multiplication by eight) and
clock-through mode. It generates four types of clocks (f
the operating clock for the CPU (f
μ
μ
μ
μ
PD70F3451
PD70F3452
PD70F3451
PD70F3452
This controller controls data transfer between on-chip peripheral I/O and internal RAM or on-chip
peripheral I/O and on-chip peripheral I/O instead of the CPU.
The transfer type is two-cycle transfer, and single transfer, single-step transfer, and block transfer are
used in transfer mode.
Part Number
Part Number
CHAPTER 1 INTRODUCTION
CPU
User’s Manual U18279EJ3V0UD
).
8 KB
12 KB
128 KB (flash memory)
256 KB (flash memory)
Internal ROM Capacity
Internal RAM Capacity
XX
, f
XX
/2, f
XX
/4, f
XX
x0000000H to x001FFFFH
x0000000H to x003FFFFH
xFFFC000H to xFFFDFFFH
xFFFC000H to xFFFEFFFH
/8), and supplies one of them as
Internal ROM Area
Internal RAM Area