UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 677

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10) AD0SCM.AD0CS bit = 0
(11) INTAD0 interrupt request signal is generated
(12) Selection trigger 1 is generated
(13) Signal of ANI05 pin is A/D-converted
(14) Shifted from buffer register 0 to buffer register 1
(15) Conversion result is stored in buffer register 0
(16) AD0SCM.AD0CS bit = 0
(17) INTAD0 interrupt request signal is generated
(18) Selection trigger 1 is generated
(19) Signal of ANI00 pin is A/D-converted
(20) Shifted from buffer register 0 to buffer register 1
(21) Conversion result is stored in buffer register 0
(22) AD0SCM.AD0CS bit = 0
(23) INTAD0 interrupt request signal is generated
AD0CE bit = 1 (enable)
Selection trigger 2 is generated
Signal of ANI02 pin is A/D-converted
Conversion result is stored in buffer register 3
AD0SCM.AD0CS bit = 0
INTAD0 interrupt request signal is generated
Selection trigger 1 is generated
Signal of ANI00 pin is A/D-converted
Conversion result is stored in buffer register 0
to buffer register 2
Figure 12-22. Example of Operation in Extension Buffer Mode: A/D Converter 0 (2/2)
CHAPTER 12 A/D CONVERTERS 0 AND 1
User’s Manual U18279EJ3V0UD
(24) Selection load trigger 1 is generated
(25) Shifted from buffer registers 0 to 2, to
(26) AD0SCM.AD0CS bit = 0
(27) Selection trigger 2 is generated
(28) Signal of ANI03 pin is A/D-converted
(29) Shifted from buffer register 3 to buffer register 4
(30) Conversion result is stored in buffer register 3
(31) AD0SCM.AD0CS bit = 0
(32) INTAD0 interrupt request signal is generated
(33) Selection trigger 1 is generated
(34) Signal of ANI05 pin is A/D-converted
(35) Shifted from buffer register 0 to buffer register 1 to
(36) Conversion result is stored in buffer register 0
(37) AD0SCM.AD0CS bit = 0
(38) INTAD0 interrupt request signal is generated
(39) Selection load trigger 2 is generated
(40) Shifted from buffer registers 3 and 4 to
(41) AD0SCM.AD0CS bit = 0
(42) When the next trigger is input, the operation is
(43) Set ADnCE bit to 0 to end (stop)
AD0ECR0 to AD0ECR2
buffer register 2
AD0ECR3 and AD0ECR4 registers
performed in accordance with that trigger.
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