UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 1040

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

22.3 Operation
1038
Clock generator:
Oscillator (f
Internal system clock (f
CPU clock (f
External bus clock (f
Clock generator:
Peripheral clock (f
Clock generator:
Watchdog timer clock (f
CPU
Internal RAM
Ports (including alternate-function pins)
On-chip peripheral I/O registers (other
than ports)
On-chip peripheral functions other than
above
(1) Reset operation by RESET pin input
Note
When a low level is input to the RESET pin, the V850E/IF3 and V850E/IG3 are reset, and each hardware unit
is initialized to a specific status.
The oscillator continues oscillation even while a low level is input to the RESET pin but the oscillation mode is
initialized to the clock-through mode (PLLCTL register = 01H) and the CPU clock (f
register = 03H).
The reset status is released when the RESET pin input goes from low to high. After the reset status is
released, the oscillation stabilization time of the oscillator and lockup time of PLL (default value of OSTS
register for the total time: 2
After release of reset, therefore, the operation is started in the clock-through mode and at f
The status of each hardware unit during the reset period and after the reset status is released is shown below.
μ
PD70F3454GC-8EA-A and 70F3454F1-DA9-A only
X
)
CPU
Hardware
)
XX
BUS
to f
CLK
)
XX
XX
Note
/1024)
/4096)
)
14
/f
X
(2.05 ms (f
Oscillation/supply continues
However, the CPU clock (f
Oscillation/supply stops
Oscillation/supply stops
Initialized
Retains value immediately before reset input only in the STOP mode during reset
input. Otherwise, undefined.
High impedance
Initialized to specific status
Stops operation
CHAPTER 22 RESET FUNCTIONS
User’s Manual U18279EJ3V0UD
During Reset Period
X
= 8 MHz)) elapse, and then the CPU starts program execution.
CPU
) is initialized to f
Oscillation/supply starts after securing of
oscillation stabilization time
Oscillation/supply starts
Program execution starts after securing
of oscillation stabilization time
Can start operation
XX
/8.
After Reset Is Released
CPU
) division to f
XX
/8.
XX
/8 (PCC