UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 668

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.4.8 A/D trigger polling mode (normal operation mode)
A/Dn conversion end interrupt request signal (INTADn) is generated.
beginning.
666
A/D conversion is started when the ADnSCM.ADnCE bit is set to 1.
When conversion is started, the ADnSCM.ADnCS bit is set to 1 (conversion is in progress).
In the A/D trigger polling mode, it is not necessary to write 1 to the ADnCE bit to restart A/D conversion after the
If the ADnSCM register is written during A/D conversion, the conversion is stopped and started again from the
(1) Operation of 1-channel conversion
Remark
Figure 12-16. Example of 1-Channel Conversion Operation (A/D Trigger Polling Mode): A/D Converter 0
(1) AD0CE bit = 1 (enable)
(2) Signal of ANI02 pin is A/D-converted
(3) Conversion result is stored in AD0CR2 register
(4) AD0SCM.AD0CS bit = 0
Remark
The signal of one analog input pin (ANInk) is converted once and the result is stored one ADnCRk register.
The ANInk pin and ADnCRk register correspond to each other on a one-to-one basis.
Each time conversion has been completed, an A/Dn conversion end interrupt request signal (INTADn) is
generated. A/D conversion is repeated until the ADnSCM.ADnCE bit is set to 0. The conversion operation is
stopped when the ADnCE bit is cleared to 0.
It is not necessary to set the ADnCE bit to restart the conversion operation in the A/D trigger polling mode.
This operation is suitable for an application where the A/D conversion value is always read.
ANInk
Analog Input Pin
AD0SCM
This is an operation example when the AD0SCM.AD0PLM, AD0TRG1, and AD0TRG0 bits = 100,
AD0CTL0.AD0MD1 and AD0CTL0.AD0MD0 bits = 00, and AD0CHEN register = 0004H.
A/D converter 0: n = 0, k = 0 to 5
A/D converter 1: n = 1, k = 0 to 7
ADnCRk
A/D Conversion Result Register
CHAPTER 12 A/D CONVERTERS 0 AND 1
ANI00
ANI01
ANI02
ANI03
ANI04
ANI05
User’s Manual U18279EJ3V0UD
(5) INTAD0 interrupt request signal is generated
(6) Return to (2)
(7) Set AD0CE bit to 0 to end (stop)
A/D converter 0
AD0CR0
AD0CR1
AD0CR2
AD0CR3
AD0CR4
AD0CR5