UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 604

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.4.6 A/D conversion start trigger output function
INTTAnCC0, INTTAnCC1) to generate the A/D conversion start trigger signal (TABTADTn0, TABTADTn1) of A/D
converters 0 and 1.
TABnOPT3.TABnAT7 bits.
ORed and output. Therefore, two or more trigger sources can be specified at the same time.
culled interrupt signals.
(TABnOPT1.TABnICE, TABnOPT1.TABnIOE bits), the A/D conversion start trigger is not output.
trigger signal depending on the status of the up-count/down-count of the 16-bit counter, if so set by the TABnAT2,
TABnAT3, TABnAT6, and TABnAT7 bits.
602
The V850E/IF3 and V850E/IG3 have a function to select four trigger sources (INTTBnOV, INTTBnCC0,
The trigger sources are specified by the TABnOPT2.TABnAT0 to TABnOPT2.TABnAT3 and TABnOPT3.TABnAT4 to
• TABnAT0, TABnAT4 bits = 1:
• TABnAT1, TABnAT5 bits = 1:
• TABnAT2, TABnAT6 bits = 1:
• TABnAT3, TABnAT7 bits = 1:
The A/D conversion start trigger signals selected by the TABnAT0 to TABnAT3 and TABnAT4 to TABnAT7 bits are
The INTTBnOV and INTTBnCC0 signals selected by the TABnAT0, TABnAT1, TABnAT4, and TABnAT5 bits are
Therefore, these signals are output after the interrupts have been culled and, unless interrupt output is enabled
The trigger sources (INTTAnCC0 and INTTAnCC1) from TAAn have a function to mask the A/D conversion start
• TABnATM2, TABnATM6 bits:
• TABnATM3, TABnATM7 bits:
• TABnATM2, TABnATM6 bits = 0
• TABnATM2, TABnATM6 bits = 1
• TABnATM3, TABnATM7 bits = 0
• TABnATM3, TABnATM7 bits = 1
The A/D conversion start trigger signal is output when the 16-bit counter counts up (TABnOPT0.TABnCUF bit
= 0), and the A/D conversion start trigger signal is not output when the 16-bit counter counts down
(TABnOPT0.TABnCUF bit = 1).
The A/D conversion start trigger signal is output when the 16-bit counter counts down (TABnOPT0.TABnCUF
bit = 1), and the A/D conversion start trigger signal is not output when the 16-bit counter counts up
(TABnOPT0.TABnCUF bit = 0).
The A/D conversion start trigger signal is output when the 16-bit counter counts up (TABnCUF bit = 0), and
the A/D conversion start trigger signal is not output when the 16-bit counter counts down (TABnCUF bit = 1).
The A/D conversion start trigger signal is output when the 16-bit counter counts down (TABnCUF bit = 1), and
the A/D conversion start trigger signal is not output when the 16-bit counter counts up (TABnCUF bit = 0).
Correspond to the TABnAT2 and TABnAT6 bits and control INTTAnCC0 (match interrupt signal) of TAAn.
Correspond to the TABnAT3 and TABnAT7 bits and control INTTAnCC1 (match interrupt signal) of TAAn.
A/D conversion start trigger signal generated when INTTBnOV (counter underflow) occurs.
A/D conversion start trigger signal generated when INTTBnCC0 (cycle match) occurs.
A/D conversion start trigger signal generated when INTTAnCC0 (match of TAAnCCR0 register of TAAn
during tuning operation) occurs.
A/D conversion start trigger signal generated when INTTAnCC1 (match of TAAnCCR1 register of TAAn
during tuning operation) occurs.
CHAPTER 10 MOTOR CONTROL FUNCTION
User’s Manual U18279EJ3V0UD