UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 381

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

• Capture operation
When the TABnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIBna pin
is detected, the count value of the 16-bit counter is stored in the TABnCCRa register, and a capture interrupt
request signal (INTTBnCCa) is generated.
The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it
generates an overflow interrupt request signal (INTTBnOV) at the next clock, is cleared to 0000H, and continues
counting. At this time, the overflow flag (TABnOPT0.TABnOVF bit) is also set to 1. Confirm that the overflow
flag is set to 1 and then clear it to 0 by executing the CLR instruction via software.
Remark
TABnCCR0 register
TABnCCR1 register
TABnCCR2 register
TABnCCR3 register
INTTBnCC0 signal
INTTBnCC1 signal
INTTBnCC2 signal
INTTBnCC3 signal
INTTBnOV signal
n = 0, 1
a = 0 to 3
TIBn0 pin input
TIBn1 pin input
TIBn2 pin input
TIBn3 pin input
16-bit counter
TABnOVF bit
Figure 7-34. Basic Timing in Free-Running Timer Mode (Capture Function)
TABnCE bit
FFFFH
0000H
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB)
0000
0000
0000
0000
D
20
D
00
D
User’s Manual U18279EJ3V0UD
30
D
10
CLR instruction
D
Cleared to 0 by
00
D
D
20
D
01
D
10
30
D
11
D
21
D
31
D
01
CLR instruction
Cleared to 0 by
D
11
D
12
D
D
21
D
02
31
D
22
D
32
D
D
Cleared to 0 by
CLR instruction
02
12
D
03
D
D
D
13
32
22
D
D
33
03
D
23
D
13
D
D
33
23
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