UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 909

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

During address transmission
Read/write data after address transmission
During extension code transmission
Read/write data after extension code transmission
During data transmission
During ACK transfer period after data reception
When restart condition is detected during data transfer
When stop condition is detected during data transfer
When the SDA pin is at low level while attempting to
generate a restart condition
When stop condition is detected while attempting to
generate a restart condition
When the SDA pin is at low level while attempting to
generate a stop condition
When the SCL pin is at low level while attempting to
generate a restart condition
17.13
extension code has been received.
addresses do not match.
addresses are transmitted due to the possibility that an arbitration loss may change the master device (which has
generated a start condition) to a slave device.
determines whether interrupt requests are enabled or disabled.
Notes 1.
The I
This function makes processing more efficient by preventing unnecessary interrupt requests from occurring when
When a start condition is detected, wakeup standby mode is set. This wakeup standby mode is in effect while
However, when a stop condition is detected, the IICC0.SPIE0 bit is set regardless of the wake up function, and this
2
C bus slave function is a function that generates an interrupt request signal (INTIIC) when a local address or
Wakeup Function
2.
When the IICC0.WTIM0 bit = 1, an interrupt request occurs at the falling edge of the ninth clock. When
the WTIM0 bit = 0 and the extension code’s slave address is received, an interrupt request occurs at
the falling edge of the eighth clock.
When there is a possibility that arbitration will occur, set the SPIE0 bit = 1 for master device operation.
Status During Arbitration
Table 17-5. Status During Arbitration and Interrupt Request Generation Timing
User’s Manual U18279EJ3V0UD
CHAPTER 17 I
At falling edge of eighth or ninth clock following byte transfer
When stop condition is generated (when IICC0.SPIE0 bit = 1)
At falling edge of eighth or ninth clock following byte transfer
When stop condition is generated (when SPIE0 bit = 1)
At falling edge of eighth or ninth clock following byte transfer
2
C BUS
Interrupt Request Generation Timing
Note 2
Note 1
Note 1
Note 1
Note 2
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