UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 432

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

430
(1) Counter basic operation
This section explains the basic operation of the 16-bit counter. For details, refer to the description of the
operation in each mode.
Remark
(a) Counter start operation
(b) Clear operation
(c) Overflow operation
• In external event count mode
• Encoder compare mode
• Triangular-wave PWM mode
• Mode other than above
The 16-bit counter is cleared to 0000H when its value matches the value of the compare register and
cleared, when the value of the 16-bit counter is captured and cleared, when the edge of the encoder clear
signal is detected and cleared, and when the clear level condition of the TENCm0, TENCm1, and TECRm
pins is detected and cleared. The count operation from FFFFH to 0000H that takes place immediately
after the counter has started counting or when the counter overflows is not a clearing operation.
Therefore, the INTTTEQCn0 and INTTTEQCn1 interrupt signals are not generated.
The 16-bit counter overflows when the counter counts up from FFFFH to 0000H in the free-running mode,
pulse width measurement mode, and encoder compare mode.
TTnOPT0.TTnOVF bit is set to 1 and an interrupt request signal (INTTTIOVn) is generated in the free-
running mode and pulse width measurement mode.
If the counter overflows, the TTnOPT1.TTnEOF bit is set to 1 and an interrupt request signal (INTTTIOVn)
is generated in the encoder compare mode.
Note that the INTTTIOVn signal is not generated under the following conditions.
• Immediately after a count operation has been started
• If the counter value matches the compare value FFFFH and is cleared
• When FFFFH is captured and cleared to 0000H in the pulse width measurement mode
When the TTmCTL0.TTmCE bit is set from 0 to 1, the 16-bit counter is set to 0000H.
After that, it counts up to 0001H, 0002H, 0003H, … each time the valid edge of external event count
input (EVTTm) is detected.
The count operation is controlled by TENCm0 and TENCm1 phases.
When the 16-bit counter initial setting is performed by transferring the set value of the TTmTCW register
to the 16-bit counter and the count operation is started. (When the TTmCTL2.TTmECC bit = 0, the
TTmTCW register set value is transferred to the 16-bit counter at the timing when the TTmCTL0.TTmCE
bit changes from 0 to 1.)
The 16-bit counter starts counting from the initial value FFFFH.
It counts up FFFFH, 0000H, 0001H, 0002H, 0003H, and so on.
Following count up operation, the counter counts down upon a match between the 16-bit count value
and the CCR0 buffer register.
The 16-bit counter starts counting from the initial value FFFFH.
It counts up FFFFH, 0000H, 0001H, 0002H, 0003H, and so on.
V850E/IF3: n = 0, 1, m = 1
V850E/IG3: n = 0, 1, m = 0, 1
CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT)
User’s Manual U18279EJ3V0UD
If the counter overflows, the