UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 989

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Maskable
Remarks 1.
Type
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Classification
2.
Default priority: The priority order when two or more maskable interrupt requests occur at the same
Restored PC:
nextPC:
The execution address of the illegal instruction when an illegal opcode exception occurs is
calculated by (Restored PC – 4).
INTCB1RE
INTCB1R
INTCB1T
INTUA2RE
INTUA2R
INTUA2T
INTCB2RE
INTCB2R
INTCB2T
INTIIC
INTAD0
INTAD1
INTAD2
INTTM0EQ0
INTTM1EQ0
INTTM2EQ0
INTTM3EQ0
INTADT0
INTADT1
CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Name
time. The highest priority is 0.
The value of the program counter (PC) saved to EIPC, FEPC, or DBPC of CPU
when interrupt servicing is started. Note, however, that the restored PC when a
non-maskable or maskable interrupt is acknowledged while one of the following
instructions is being executed does not become the nextPC. (If an interrupt is
acknowledged during interrupt execution, execution stops, and then resumes after
the interrupt servicing has finished.
instruction is the restore PC.)
• Load instructions (SLD.B, SLD.BU, SLD.H, SLD.HU, SLD.W)
• Division instructions (DIV, DIVH, DIVU, DIVHU)
• PREPARE, DISPOSE instructions (only if an interrupt is generated before the
The PC value that starts the processing following interrupt/exception processing.
CB1REIC
CB1RIC
CB1TIC
UA2REIC
UA2RIC
UA2TIC
CB2REIC
CB2RIC
CB2TIC
IICIC
AD0IC
AD1IC
AD2IC
TM0EQIC0
TM1EQIC0
TM2EQIC0
TM3EQIC0
ADT0IC
ADT1IC
stack pointer is updated)
Table 20-1. Interrupt Source List (4/4)
Register
Control
Interrupt/Exception Source
User’s Manual U18279EJ3V0UD
CSIB1 reception error
CSIB1 reception end
CSIB1 transmission enable
UARTA2 reception error
UARTA2 reception end
UARTA2 transmission enable UARTA2
CSIB2 reception error
CSIB2 reception end
CSIB2 transmission enable
IIC serial transfer end
ADC0 conversion end
ADC1 conversion end
ADC2 conversion end
TM0CMP0 compare match
TM1CMP0 compare match
TM2CMP0 compare match
TM3CMP0 compare match
ADTRG0 pin valid edge
input
ADTRG1 pin valid edge
input
Generating Source
CSIB1
CSIB1
CSIB1
UARTA2
UARTA2
CSIB2
CSIB2
CSIB2
IIC
ADC0
ADC1
ADC2
TMM0
TMM1
TMM2
TMM3
Pin
Pin
Generating
In this case, the address of the aborted
Unit
Default
Priority
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Exception
0540H
0550H
0560H
0570H
0580H
0590H
05A0H
05B0H
05C0H
05D0H
05E0H
05F0H
0600H
0610H
0620H
0630H
0640H
0650H
0660H
Code
00000540H nextPC
00000550H nextPC
00000560H nextPC
00000570H nextPC
00000580H nextPC
00000590H nextPC
000005A0H nextPC
000005B0H nextPC
000005C0H nextPC
000005D0H nextPC
000005E0H nextPC
000005F0H nextPC
00000600H nextPC
00000610H nextPC
00000620H nextPC
00000630H nextPC
00000640H nextPC
00000650H nextPC
00000660H nextPC
Address
Handler
Restored
PC
987