UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 764

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

762
Note After receive FIFO (UBRXAP) is cleared (UBRFC bit = 1), accessing the registers related to UARTB is
Remark
prohibited for the duration of four cycles of f
confirmed by reading the UBFIC0 register.
guaranteed.
f
XX
: Peripheral clock
UBRFC
In the FIFO mode, the INTUBTIR signal is generated as soon as receive data of the
number set as the trigger by the UBFIC2.UBRT3 to UBFIC2.UBRT0 bits have been
transferred from the receive shift register to receive FIFO. After the INTUBTIR
signal request has been generated, specify the timing of actually generating the
INTUBTIR signal as the pending mode or pointer mode. For details, see 15.6 (2)
Pending mode/pointer mode.
•
•
•
UBITM
In the FIFO mode, the INTUBTIT signal is generated as soon as transmit data of the
number set as the trigger by the UBFIC2.UBTT3 to UBFIC2.UBTT0 bits have been
transferred from transmit FIFO to the transmit shift register. After the INTUBTIT
signal request has been generated, specify the timing of actually generating the
INTUBTIT signal as the pending mode or pointer mode. For details, see 15.6 (2)
Pending mode/pointer mode.
UBIRM
The UBRFC bit is valid only in the FIFO mode (UBMOD bit = 1), and is invalid in
the single mode (UBMOD bit = 0).
When 1 is written to the UBRFC bit, the pointer to receive FIFO is cleared to 0.
In the pending mode (UBIRM bit = 0), the interrupt request signal (INTUBTIR)
held pending is cleared
register (URIC) is not cleared to 0. Clear this bit to 0 as necessary.
When 0 is written to the UBRFC bit, the status is retained. No operation, such
as clearing or setting, is executed.
When writing 1 to the UBRFC bit, be sure to clear the UBCTL0.UBRXE bit to 0
(disabling reception). If 1 is written to the UBRFC bit when the UBRXE bit is 1
(reception enabled), the operation is not guaranteed.
0
1
0
1
0
1
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE B (UARTB)
Normal status
Clear (This bit automatically returns to 0 after receive FIFO is cleared.)
Pending mode
Pointer mode
Pending mode
Pointer mode
Specification of INTUBTIR interrupt generation timing in FIFO mode
Specification of INTUBTIT interrupt generation timing in FIFO mode
Note
Receive FIFO (UBRXAP) clear trigger bit
User’s Manual U18279EJ3V0UD
. However, bit 7 (URIF) of the interrupt control
XX
If these registers are accessed, the operation is not
or until clearing the UBRFC bit (automatic recovery) is
(2/2)