UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 1185

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Mnemonic
SUB
SUBR
SWITCH
SXB
SXH
TRAP
TST
TST1
XOR
XORI
ZXB
ZXH
Notes 1.
reg1,reg2
reg1,reg2
reg1
reg1
reg1
vector
reg1,reg2
bit#3,disp16[reg1]
reg2, [reg1]
reg1,reg2
imm16,reg1,reg2
reg1
reg1
10. b: bit 0 of disp16.
11. According to the number of wait states (2 if there are no wait states).
2.
3.
4.
5.
6.
7.
8.
9.
Operand
dddddddd: Higher 8 bits of disp9.
4 if there is an instruction that rewrites the contents of the PSW immediately before.
If there is no wait state (3 + the number of read access wait states).
n is the total number of list12 load registers. (According to the number of wait states. Also, if there
are no wait states, n is the total number of list12 registers. If n = 0, same operation as when n = 1)
RRRRR: other than 00000.
The lower halfword data only are valid.
ddddddddddddddddddddd: The higher 21 bits of disp22.
ddddddddddddddd: The higher 15 bits of disp16.
According to the number of wait states (1 if there are no wait states).
r r rr r0 01 10 1 RRRRR GR[reg2]←GR[reg2]–GR[reg1]
r r rr r0 01 10 0 RRRRR GR[reg2]←GR[reg1]–GR[reg2]
00000000010RRRRR adr←(PC+2) + (GR[reg1] logically shift left by 1)
00000000101RRRRR GR[reg1]←sign-extend
00000000111RRRRR GR[reg1]←sign-extend
0 0 0 0 0 1 1 1 1 1 1 i i i i i
0000000100000000
r r rr r0 01 01 1 RRRRR result←GR[reg2] AND GR[reg1]
11bbb111110RRRRR
dddddddddddddddd
r r rr r1 11 11 1 RRRRR
0000000011100110
r r rr r0 01 00 1 RRRRR GR[reg2]←GR[reg2] XOR GR[reg1]
r r rr r1 10 10 1 RRRRR
i i i i i i i i i i i i i i i i
00000000100RRRRR GR[reg1]←zero-extend(GR[reg1] (7:0))
00000000110RRRRR GR[reg1]←zero-extend(GR[reg1] (15:0))
Opcode
APPENDIX C INSTRUCTION SET LIST
User’s Manual U18279EJ3V0UD
PC←(PC+2) + (sign-extend
(Load-memory(adr,Halfword))
logically shift left by 1
(GR[reg1] (7:0))
(GR[reg1] (15:0))
EIPC
EIPSW
ECR.EICC ←Exception code
PSW.EP
PSW.ID
PC
adr←GR[reg1]+sign-extend(disp16)
Z flag←Not(Load-memory-bit(adr,bit#3))
adr←GR[reg1]
Z flag←Not(Load-memory-bit(adr,reg2))
GR[reg2]←GR[reg1] XOR zero-extend(imm16)
←PC+4(return PC)
←PSW
←1
←1
←00000040H
(40H to 4FH, 50H to 5FH)
(when vector is 00H to 0FH
(exception code: 40H to 4FH))
00000050H
(when vector is 10H to 1FH
(exception code: 50H to 5FH))
Operation
Note 3
Note 3
1
1
5
1
1
4
1
3
3
1
1
1
1
Execution
i
Clock
Note 3
Note 3
1
1
5
1
1
4
1
3
3
1
1
1
1
r
Note 3
Note 3
1
1
5
1
1
4
1
3
3
1
1
1
1
l
CY OV S
×
×
×
×
0
0
0
Flags
×
×
×
×
×
Z SAT
×
×
×
×
×
×
×
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