UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 776

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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(ii) During reception (reading from receive FIFO)
• Each time the data of 1 byte is transferred to receive FIFO from the receive shift register, a
• In the pointer mode, be sure to fix the UBFIC2.UBRT3 to UBFIC2.UBRT0 bits to 0000 (set number
• Reading receive data from receive FIFO by DMA is prohibited. The operation is not guaranteed if
• After the reception end interrupt request signal (INTUBTIR) has been acknowledged, data of the
reception end interrupt request signal (INTUBTIR) occurs.
of receive data: 1 byte) as the number of receive data set as the trigger for receive FIFO when the
reception end interrupt request signal (INTUBTIR) occurs.
operation is not guaranteed.
DMA control is used.
number of bytes stored in receive FIFO can be read from receive FIFO by referencing the UBFIS0
register. In some cases, however, data is not stored in receive FIFO even though the INTUBTIR
signal is generated (UBFIS0.UBRB4 to UBFIS0.UBRB0 bits = 00000). In these cases, do not read
data from receive FIFO. Always read data from receive FIFO when the number of bytes stored in
receive FIFO is 1 byte or more (UBRB4 to UBRB0 bits = other than 00000).
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE B (UARTB)
User’s Manual U18279EJ3V0UD
If any other setting is made, the