UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 414

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

412
Cautions 1. The TTmECC bit is valid only in the encoder compare mode. In any other mode, writing “1”
2. The TTmLDE bit is valid only when the TTmECM1 and TTmECM0 bits = 00, 01. Writing “1”
3. The edge detection of the TENCm0 and TENCm1 inputs specified by the TTmIOC3.TTmEIS1
4. Set the TTmLDE, TTmECM1, TTmECM0, TTmUDS1, and TTmUDS0 bits when the
5. Be sure to set bits 5 and 6 to “0”.
to this bit is ignored.
If the TTmCTL0.TTmCE bit is cleared to 0 while the TTmECC bit = 1, the values of the
timer/counter and capture registers (TTmCCR0 and TTmCCR1), and the TTmOPT1,
TTmEUF, TTmEOF, and TTmESF flags are retained.
If the TTmCE bit is set from 0 to 1 when the TTmECC bit = 1, the value of the TTmTCW
register is not transferred to the 16-bit counter.
to this bit is ignored when the TTmECM1 and TTmECM0 bits = 10, 11.
and TTmIOC3.TTmEIS0 bits is invalid and fixed to both the rising and falling edges when
the TTmUDS1 and TTmUDS0 bits = 10, 11.
TTmCTL0.TTmCE bit = 0 (the same value can be written to these bits when the TTmCE bit =
1). If the value of these bits is changed when the TTmCE bit = 1, the operation cannot be
guaranteed. If it is changed by mistake, clear the TTmCE bit and then set the correct value.
TTmUDS1
0
0
1
1
TTmUDS0
CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT)
0
1
0
1
When valid edge of TENCm0 input is detected
Counts down when TENCm1 = high level.
Counts up when TENCm1 = low level.
Counts up when valid edge of TENCm0 input is detected.
Counts down when valid edge of TENCm1 input is detected.
Counts down when rising edge of TENCm0 input is detected.
Counts up when falling edge of TENCm0 input is detected.
However, count operation is performed only when
TENCm1 = low level.
Both rising and falling edges of TENCm0 and TENCm1 are
detected. Count operation is automatically identified by
combination of edge detection and level detection.
User’s Manual U18279EJ3V0UD
Up/down count selection
(2/2)