UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 913

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.14.2 When communication reservation function is disabled (IICF0.IICRSV0 bit = 1)
request is rejected and a start condition is not generated. The following two statuses are included in the status where
bus is not used.
time shown in Table 17-7 is required until the STCF0 flag is set after setting the STT0 bit = 1. Therefore, secure the
time by software.
When the IICC0.STT0 bit is set when the bus is not used in a communication during bus communication, this
• When arbitration results in neither master nor slave operation
• When an extension code is received and slave operation is disabled (ACK is not returned and the bus was
To confirm whether the start condition was generated or request was rejected, check the IICF0.STCF0 flag. The
released when the IICC0.LREL0 bit was set to 1)
f
f
f
f
f
f
XX
XX
XX
XX
XX
XX
/8 (IICOCKS = 12H)
/10 (IICOCKS = 13H)
/4 (IICOCKS = 10H)
/6 (IICOCKS = 11H)
/8 (IICOCKS = 12H)
/10 (IICOCKS = 13H)
Selection Clock
CLX0
0
0
0
0
0
0
Table 17-7. Wait Periods
User’s Manual U18279EJ3V0UD
SMC0
CHAPTER 17 I
0
0
0
0
0
0
CL00
0
0
1
1
1
1
2
C BUS
5 clocks
5 clocks
5 clocks
5 clocks
5 clocks
5 clocks
Wait Clock
0.63
0.78
0.31
0.47
0.63
0.78
When f
μ
μ
μ
μ
μ
μ
Wait Time
s
s
s
s
s
s
XX
= 64 MHz
911