UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 740

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.7 Dedicated Baud Rate Generator
and generates a serial clock during transmission and reception with UARTAn. Regarding the serial clock, a dedicated
baud rate generator output can be selected for each channel.
738
The dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable counter,
There is an 8-bit counter for transmission and another one for reception.
(1) Baud rate generator configuration
(a) Base clock
(b) Serial clock generation
Caution If the CPU clock (f
Remarks 1. n = 0 to 2
When the UAnCTL0.UAnPWR bit is 1, the clock selected by the UAnCTL1.UAnCKS3 to
UAnCTL1.UAnCKS0 bits is supplied to the 8-bit counter. This clock is called the base clock (f
the UAnPWR bit = 0, f
A serial clock can be generated by setting the UAnCTL1 register and the UAnCTL2 register.
The base clock (f
The frequency division value for the 8-bit counter can be set using the UAnCTL2.UAnBRS7 to
UAnCTL2.UAnBRS0 bits.
f
f
f
XX
XX
XX
f
f
f
XX
XX
XX
f
f
f
/1024
/2048
/4096
XX
XX
XX
f
f
f
/128
/256
/512
XX
XX
XX
/16
/32
/64
/2
/4
/8
2. f
UAnCKS3 to UAnCKS0
XX
: Peripheral clock frequency
UAnPWR bit
UAnCTL1:
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
Selector
UCLK
Figure 14-12. Configuration of Baud Rate Generator
) is selected by the UAnCTL1.UAnCKS3 to UAnCTL1.UAnCKS0 bits.
UCLK
CPU
is fixed to the low level.
) is slower than f
f
UCLK
UAnPWR, UAnTXE bit
User’s Manual U18279EJ3V0UD
UAnBRS7 to UAnBRS0
Match detector
8-bit counter
UAnCTL2:
UCLK
, UARTAn cannot be used.
(or UAnRXE bit)
Output clock
1/2
Baud rate
UCLK
). When