UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 259

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOAm1
pin. After the one-shot pulse is output, the 16-bit counter is cleared to 0000H, stops counting, and waits for a trigger.
When the trigger is generated again, the 16-bit counter starts counting from 0000H. If a trigger is generated again
while the one-shot pulse is being output, it is ignored.
count value matches the value of the CCR0 buffer register. The compare match interrupt request signal (INTTAmCC1)
is generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register.
1 is used as the trigger.
When the TAAmCE bit is set to 1, 16-bit timer/event counter AA waits for a trigger. When the trigger is generated,
The output delay period and active level width of the one-shot pulse can be calculated as follows.
The compare match interrupt request signal (INTTAmCC0) is generated when the 16-bit counter counts after its
The valid edge of an external trigger input (TIAm0 pin) or setting the software trigger (TAAmCTL1.TAAnEST bit) to
Remark
External trigger input
TAAmCCR0 register
TAAmCCR1 register
(only when software
INTTAmCC0 signal
INTTAmCC1 signal
TOAm0 pin output
TOAm1 pin output
Output delay period = (Set value of TAAmCCR1 register) × Count clock cycle
Active level width = (Set value of TAAmCCR0 register − Set value of TAAmCCR1 register + 1) × Count clock
(TIAm0 pin input)
trigger is used)
16-bit counter
TAAmCE bit
V850E/IF3: m = 2, 4
V850E/IG3: m = 2 to 4
FFFFH
0000H
cycle
Figure 6-29. Basic Timing in One-Shot Pulse Output Mode
CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA)
Delay
(D
D
1
1
)
Active
level width
(D
D
User’s Manual U18279EJ3V0UD
0
0
− D
1
+ 1)
Delay
(D
D
1
1
)
Active
level width
(D
D
D
D
0
0
1
0
− D
1
+ 1)
Delay
(D
D
1
1
)
Active
level width
(D
D
0
0
− D
1
+ 1)
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