UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 820

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

818
(4) CSIBn status register (CBnSTR)
Caution In single transfer mode, writing to the CBnTX register with the CBnTSF bit set to 1 is ignored.
CBnSTR is an 8-bit register that displays the CSIBn status.
This register can be read or written in 8-bit or 1-bit units, but the CBnTSF flag is read-only.
Reset sets this register to 00H.
In addition to reset, the CBnSTR register can be initialized by clearing (0) the CBnCTL0.CBnPWR bit.
This has no influence on the operation during transfer.
For example, if the next data is written to the CBnTX register when DMA is started by
generating the INTCBnR signal, the written data is not transferred because the CBnTSF bit is
set to 1.
Use the continuous transfer mode, not the single transfer mode, for such applications.
(n = 0 to 2)
CBnSTR
After reset: 00H
• An overrun error occurs when the next reception starts without performing a CPU
• The CBnOVE flag is cleared by writing 0 to it. It cannot be set even by writing 1 to it.
CBnOVE
CBnTSF
• During transmission, this register is set when data is prepared in the CBnTX
CBnTSF
read of the value of the CBnRX register, upon end of the receive operation.
The CBnOVE flag displays the overrun error occurrence status in this case.
register, and during reception, it is set when a dummy read of the CBnRX register
is performed.
When transfer ends, this flag is cleared to 0 at the last edge of the clock.
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CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB)
0
1
0
1
R/W
Communication stopped
Communicating
No overrun
Overrun
0
Address: CB0STR FFFFFD03H, CB1STR FFFFFD13H,
User’s Manual U18279EJ3V0UD
0
CB2STR FFFFFD23H
Communication status flag
0
Overrun error flag
0
0
0
CBnOVE
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