UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 263

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) Operation timing in one-shot pulse output mode
External trigger input
TAAmCCR0 register
TAAmCCR1 register
(only when software
INTTAmCC0 signal
INTTAmCC1 signal
TOAm0 pin output
TOAm1 pin output
(TIAm0 pin input)
(a) Note on rewriting TAAmCCRa register
trigger is used)
16-bit counter
TAAmCE bit
If the value of the TAAmCCRa register is rewritten to a smaller value during counting, the 16-bit counter
may overflow. When an overflow may occur, stop counting and then change the set value.
When the TAAmCCR0 register is rewritten from D
where D
counter is greater than D
value is greater than D
rewritten and compared with the count value. The counter counts up to FFFFH and then counts up again
from 0000H. When the count value matches D
asserts the TOAm1 pin output.
INTTAmCC0 signal, deasserts the TOAm1 pin output, and stops counting.
Therefore, the counter may output a pulse with a delay period or active period different from that of the
one-shot pulse that is originally expected.
Remark
FFFFH
0000H
00
V850E/IF3: m = 2, 4, a = 0, 1
V850E/IG3: m = 2 to 4, a = 0, 1
> D
01
and D
CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA)
01
10
11
and less than D
> D
Delay
(D
and less than D
10
D
11
)
10
, if the TAAmCCR1 register is rewritten when the count value of the 16-bit
Active level width
(D
00
User’s Manual U18279EJ3V0UD
D
− D
00
When the count value matches D
10
+ 1)
D
00
10
, each set value is reflected as soon as the register has been
10
D
Delay
(D
00
and if the TAAmCCR0 register is rewritten when the count
10
D
)
11
10
00
Active level width
(D
, the counter generates the INTTAmCC1 signal and
00
to D
D
− D
00
01
10
+ 1)
and the TAAmCCR1 register from D
D
10
Delay
(10000H + D
01
D
, the counter generates the
00
11
)
D
D
D
Active level width
(D
11
11
01
D
01
01
− D
11
+ 1)
10
to D
261
11