UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 762

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

760
Cautions 3. Do not perform the following operations when debugging a system that uses the single
UBRXAP
After reset: 00FFH
After reset: FFH
UBRX
mode.
• Setting a break for an instruction immediately after the UBRX register is read
• Setting a break before DMA transfer with the UBRX register specified as the transfer
• Setting a break before end of reception of the next data after reception of data and
If any of these operations is performed, an overrun error may occur during the
subsequent reception.
source is ended
reading the UBRX register, and checking the UBRX register in the I/O register window
of the debugger
UBRD7 to
UBRD0
15
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE B (UARTB)
UBRD7
•
•
•
•
UBPEF
UBFEF
0
The UBPEF bit is valid only in the FIFO mode (UBFIC0.UBMOD bit = 1), and is
invalid in the single mode (UBFIC0.UBMOD bit = 0).
The operation of the UBPEF bit differs depending on the set values of the
UBCTL0.UBPS1 and UBCTL0.UBPS0 bits.
The UBFEF bit is valid only in the FIFO mode (UBFIC0.UBMOD bit = 1), and is
invalid in the single mode (UBFIC0.UBMOD bit = 0).
Only the first bit of the stop bits of the receive data is checked, regardless of the
stop bit length.
7
0
1
0
1
14
0
No parity error
Parity error occurs (during reception).
No framing error
Framing error occurs (during reception).
Stores receive data.
13
UBRD6
R
0
R
6
12
0
Address: FFFFFA46H
Address: FFFFFA46H
11
UBRD5
User’s Manual U18279EJ3V0UD
0
5
10
0
PEF
UB
UBRD4
9
4
FEF
UB
Framing error flag
8
Parity error flag
RD7
UB
UBRD3
7
3
RD6
UB
6
RD5
UB
UBRD2
5
2
RD4
UB
4
RD3
UB
UBRD1
3
1
RD2
UB
2
RD1
UB
UBRD0
1
0
RD0
UB
0