UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 1058

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

26.1.2 Interface signals
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The interface signals on the V850E/IG3 side are described below.
(1) DRST
(2) DCK
(3) DMS
(4) DDI
(5) DDO
(6) FLMD0
This is a reset input signal for the on-chip debug unit. It is a negative-logic signal that asynchronously
initializes the debug control unit (DCU).
MINICUBE changes the level of the DRST signal from low to high for output and starts the on-chip debug unit
of the V850E/IG3 when it detects VDD of the target system after the integrated debugger is started. If VDD is
not detected from the target system, the output signals (DRST, DCK, DMS, DDI, and FLMD0 pins) from the
MINICUBE go into a high-impedance state.
When the DRST signal goes high, a reset signal is also generated in the V850E/IG3.
When starting debugging by starting the integrated debugger, a reset signal is always generated.
This is a clock input signal. It supplies a 20 MHz clock from MINICUBE. In the on-chip debug unit, the DMS
and DDI signals are sampled at the rising edge of the DCK signal, and the data DDO is output at its falling
edge.
This is a transfer mode select signal. The transfer status in the debug unit changes depending on the level of
the DMS signal.
This is a data input signal. It is sampled in the on-chip debug unit at the rising edge of DCK.
This is a data output signal. It is output from the on-chip debug unit at the falling edge of the DCK signal.
The flash self programming function is used for the function to download data to the flash memory via the
integrated debugger. During flash self programming, the FLMD0 pin must be kept high. In addition, connect a
pull-down resistor to the FLMD0 pin.
The FLMD0 pin can be controlled in either of the following two ways.
<1> To control from MINICUBE
<2> To control from port
Connect the FLMD0 signal of MINICUBE to the FLMD0 pin of the V850E/IG3.
In the normal mode, nothing is driven by MINICUBE (high impedance).
During a break, MINICUBE raises the FLMD0 pin to the high level when the download function of the
integrated debugger is executed.
Connect any port of the device to the FLMD0 pin of the V850E/IG3.
The same port as the one used by the user program to realize the flash self programming function may
be used.
On the console of the integrated debugger, make a setting to raise the port pin to high level before
executing the download function, or lower the port pin after executing the download function.
For details, refer to the ID850QB Integrated Debugger Operation User’s Manual.
CHAPTER 26 ON-CHIP DEBUG FUNCTION
User’s Manual U18279EJ3V0UD