UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 775

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(b) Pointer mode
(ii) During reception (reading from receive FIFO)
(i) During transmission (writing to transmit FIFO)
• If data for the first reception end interrupt request signal (INTUBTIR) is not read from receive FIFO,
• In the pending mode, receive data of the number set as the trigger by the UBFIC2.UBRT3 to
• Fix the UBFIC2.UBRT3 to UBFIC2.UBRT0 bits to 0000 (set number of receive data: 1 byte) to
• Each time the data of 1 byte is transferred to the transmit shift register from transmit FIFO, a
• In the pointer mode, be sure to fix the UBFIC2.UBTT3 to UBFIC2.UBTT0 bits to 0000 (set number
• Writing transmit data to transmit FIFO by DMA is prohibited. The operation is not guaranteed if
• After the transmission enable interrupt request signal (INTUBTIT) has been acknowledged, data of
the second INTUBTIR signal does not occur (is held pending) even if the generation condition of
the second INTUBTIR is satisfied (if receive data of the number set as the trigger by the
UBFIC2.UBRT3 to UBFIC2.UBRT0 bits can be read from receive FIFO). When data for the first
INTUBTIR signal is later read from the receive FIFO, the pending INTUBTIR signal is generated
Note The number of pending interrupts is as follows.
UBFIC2.UBRT0 bits is always read from receive FIFO when the reception end interrupt request
signal (INTUBTIR) occurs. Reading data from receive FIFO is prohibited if the data is more or less
than the specified number. If data more or less than the specified number is read, the operation is
not guaranteed.
read receive data from receive FIFO by DMA. If any other setting is made, the operation is not
guaranteed.
transmission enable interrupt request signal (INTUBTIT) occurs.
of transmit data: 1 byte) as the number of transmit data set as the trigger for transmit FIFO when
the transmission enable interrupt request signal (INTUBTIT) occurs. If any other setting is made,
the operation is not guaranteed.
DMA control is used.
the number of empty bytes of transmit FIFO can be written to transmit FIFO by referencing the
UBFIS1 register.
When trigger is set to 1 byte (UBFIC2.UBRT3 to UBFIC2.UBRT0 bits = 0000): 15 times max.
When trigger is set to 2 bytes (UBFIC2.UBRT3 to UBFIC2.UBRT0 bits = 0001): 7 times max.
When trigger is set to 6 bytes (UBFIC2.UBRT3 to UBFIC2.UBRT0 bits = 0101): 1 time max.
When trigger is set to 7 bytes (UBFIC2.UBRT3 to UBFIC2.UBRT0 bits = 0110): 1 time max.
When trigger is set to 8 bytes (UBFIC2.UBRT3 to UBFIC2.UBRT0 bits = 0111): 1 time max.
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE B (UARTB)
User’s Manual U18279EJ3V0UD
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773
Note
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