UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 752

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

750
(7) UARTB FIFO status register 0 (UBFIS0)
(8) UARTB FIFO status register 1 (UBFIS1)
(9) Receive shift register
(10) UARTB receive data register AP (UBRXAP), UARTB receive data register (UBRX)
(11) Transmit shift register
This register is valid in the FIFO mode. The number of bytes of data stored in the receive FIFO can be read
from this register.
This register is valid in the FIFO mode. The number of empty bytes of the transmit FIFO can be read from
this register.
This is a shift register that converts the serial data that was input to the RXDB pin into parallel data. One byte
of data is received, and if a stop bit is detected, the received data is transferred to the receive data register.
This register cannot be directly manipulated.
The receive data register holds receive data. In the single mode, the 8-bit × 1-stage UBRX register is used.
The 16-bit × 16-stage receive FIFO (UBRXAP register) is used in the FIFO mode.
The receive data is stored in the lower 8 bits of the receive FIFO (UBRXAP register) and the error information
of the received data is stored in the higher 8 bits (bit 8 and bit 9). If a reception error (such as a parity error or
a framing error) occurs in the FIFO mode, the error data can be identified by reading the UBRXAP register in
16-bit (halfword) units (error information is appended as UBPEF bit = 1 or UBFEF bit = 1). When the lower 8
bits of the UBRXAP register are read in 8-bit (byte) units, the higher 8 bits are discarded. Therefore, if no
error has occurred, only the receive data of the UBRXAP register can be read successively by being read in
8-bit (byte) units in the same way as the UBRX register.
When 7-bit length data is received with the LSB first, the received data is transferred to bits 6 to 0 of the
receive data register from the LSB (bit 0), with the MSB (bit 7) always being 0. When data is received with
the MSB first, the received data is transferred to bits 7 to 1 of the receive data register from the MSB (bit 7),
with the LSB (bit 0) always being 0. If an overrun error occurs, the receive data at that time is not transferred
to the receive data register.
While reception is enabled, the received data is transferred from the receive shift register to the receive data
register, in synchronization with the shift-in processing of one frame.
A reception end interrupt request signal (INTUBTIR) is generated by transferring the data to the UBRX
register in the single mode, or transferring the number of receive data set as the trigger by the
UBFIC2.UBRT3 to UBFIC2.UBRT0 bits to receive FIFO in the FIFO mode. If data is stored in receive FIFO
when the next data does not come (start bit is not detected) after the next data reception wait time specified
by the UBFIC1.UBTC4 to UBFIC1.UBTC0 bits has elapsed in the FIFO mode, a reception timeout interrupt
request signal (INTUBTITO) is generated.
This is a shift register that converts the parallel data that was transferred from the transmit data register into
serial data.
When one byte of data is transferred from the transmit data register, the transmit shift register data is output
from the TXDB pin.
This register cannot be directly manipulated.
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE B (UARTB)
User’s Manual U18279EJ3V0UD