UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 96

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

94
(1) Setting data to special registers
Cautions 1. When a store instruction is executed to store data in the command register, interrupts are
Set data to the special registers in the following sequence.
<1> Prepare data to be set to the special register in a general-purpose register.
<2> Write the data prepared in <1> to the command register.
<3> Write the setting data to the special register (by using the following instructions).
(<4> to <8> Insert NOP instructions (5 instructions).)
There is no special sequence to read a special register.
Note Five NOP instructions or more must be inserted immediately after setting the IDLE mode or STOP
[Example] With PSC register (setting standby mode)
<1>MOV 0x02, r10
<2>ST.B r10, PRCMD[r0] ; Write PRCMD register.
<3>ST.B r10, PSC[r0]
<4>NOP
<5>NOP
<6>NOP
<7>NOP
<8>NOP
(next instruction)
• Store instruction (ST/SST instruction)
• Bit manipulation instruction (SET1/CLR1/NOT1 instruction)
ST.B r11, PSMR[r0]
mode (by setting the PSC.STB bit to 1).
Note
Note
Note
Note
Note
2. Although dummy data is written to the command register, use the same general-purpose
3. Before executing this processing, terminate all DMA transfer operations.
not acknowledged. This is because it is assumed that steps <2> and <3> above are
performed by successive store instructions. If another instruction is placed between <2>
and <3>, and if an interrupt is acknowledged by that instruction, the above sequence may
not be established, causing malfunction.
register used to set the special register (<3> in Example) by using the store instruction to
write data to the command register (<2> in Example). The same applies when a general-
purpose register is used for addressing.
An example of setting the special register (<3> in Example) by using the bit manipulation
instruction is shown below.
CLR1 4, RESF[r0]
; Set PSMR register (setting IDLE and STOP modes).
; Set PSC register.
; Dummy instruction
; Dummy instruction
; Dummy instruction
; Dummy instruction
; Dummy instruction
CHAPTER 3 CPU FUNCTION
User’s Manual U18279EJ3V0UD
Note