UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 1017

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.5 Software Exception
acknowledged.
20.5.1 Operation
routine.
becomes 00000040H, and if the vector is 10H to 1FH, it becomes 00000050H.
A software exception is generated when the CPU executes the TRAP instruction, and can always be
If a software exception occurs, the CPU performs the following processing, and transfers control to the handler
<1> Saves the restored PC to EIPC.
<2> Saves the current PSW to EIPSW.
<3> Writes an exception code to the lower 16 bits (EICC) of ECR (interrupt source).
<4> Sets the PSW.EP and PSW.ID bits (1).
<5> Sets the handler address (00000040H or 00000050H) corresponding to the software exception to the PC,
The processing of a software exception is shown below.
The handler address is determined by the TRAP instruction’s operand (vector). If the vector is 00H to 0FH, it
Note TRAP instruction format: TRAP vector (the vector is a value from 00H to 1FH.)
and transfers control.
CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION
CPU processing
Figure 20-8. Software Exception Processing
User’s Manual U18279EJ3V0UD
EIPC
EIPSW
ECR.EICC
PSW.EP
PSW.ID
PC
Exception processing
TRAP instruction
Restored PC
PSW
Exception code
1
1
Handler address
Note
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