UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 785

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.7.5 Reception error
are a parity error, framing error, and overrun error. In the FIFO mode (UBFIC0.UBMOD bit = 1), the three types of
errors that can occur during a receive operation are a parity error, framing error, and overflow error.
framing error, or overrun error occurs in the single mode. The UBSTR.UBOVF bit is set to 1 if an overflow error occurs
in the FIFO mode. The UBRXAP.UBPEF or UBRXAP.UBFEF bit is set to 1 if a parity error or framing error occurs in
the FIFO mode. At the same time, a reception error interrupt request signal (INTUBTIRE) occurs. The contents of the
error can be detected by reading the contents of the UBSTR or UBRXAP register.
UBCTL0.UBPWR or UBCTL0.UBRXE bit. The contents of the UBRXAP register are reset when 0 is written to the
UBCTL0.UBPWR bit.
UBPE
UBFE
UBOVE
UBOVF
UBPEF
UBFEF
In the single mode (UBFIC0.UBMOD bit = 0), the three types of errors that can occur during a receive operation
As a result of data reception, the UBSTR.UBPE, UBSTR.UBFE, or UBSTR.UBOVE bit is set to 1 if a parity error,
The contents of the UBSTR register are reset when 0 is written to the UBOVF, UBPE, UBFE, or UBOVE bit, or the
Error Flag
Single mode
FIFO mode
Valid Operation
Mode
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE B (UARTB)
UBPE
UBFE
UBOVE
UBOVF
UBPEF
UBFEF
Error Flag
Table 15-4. Reception Error Causes
User’s Manual U18279EJ3V0UD
Parity error
Overrun error
Framing error
Overflow error
Parity error
Framing error
Reception Error
The parity specification during transmission does
not match the parity of the receive data
No stop bit detected
The reception of the next data is ended before
data is read from the UBRX register
receive FIFO is full and before data is read.
The parity specification during transmission does
not match the parity of the data to be received.
The stop bit is not detected when the target data
is loaded.
The reception of the next data is ended while
Cause
783