UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 873

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Remark x: don’t care
IICX0
CLX0
Bit 0
(7) I
0
0
0
1
1
For example, the I
calculated using following expression.
The selection clock is set using a combination of the IICCL0.SMC0, IICCL0.CL00, IICX0.CLX0,
IICOCKS.IICOCKS1, and IICOCKS.IICOCKS0 bits.
The I
2
C transfer clock setting method
SMC0
Bit 3
f
SCL
0
0
1
0
1
2
m = 96, 120, 144, 192, 240, 344, 352, 440, 516, 688, 860 (see Table 17-2 Selection Clock Setting.)
T: 1/f
t
t
f
C transfer clock frequency (f
R
F
SCL
IICCL0
: SCL fall time
: SCL rise time
= 1/(m × T + t
= 1/(192 × 15.6 ns + 200 ns + 50 ns) ≅ 308 kHz
CL00
XX
Bit 0
0
1
x
x
x
SCL
2
C transfer clock frequency (f
SCL inversion
f
f
f
f
f
f
f
f
f
f
Setting prohibited
f
f
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
R
/8 (when IICOCKS = 12H)
/10 (when IICOCKS = 13H)
/4 (when IICOCKS = 10H)
/6 (when IICOCKS = 11H)
/8 when (IICOCKS = 12H)
/10 (when IICOCKS = 13H)
/4 (when IICOCKS = 10H)
/6 (when IICOCKS = 11H)
/8 (when IICOCKS = 12H)
/10 (when IICOCKS = 13H)
/8 (when IICOCKS = 12H)
/10 (when IICOCKS = 13H)
t
R
+ t
F
Selection Clock
)
m/2 × T
Table 17-2. Selection Clock Setting
SCL
) is calculated using the following expression.
User’s Manual U18279EJ3V0UD
m × T + t
CHAPTER 17 I
SCL inversion
SCL
R
Transfer Clock
) when f
f
f
f
f
f
f
f
f
f
f
f
f
+ t
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
/352
/440
/344
/516
/688
/860
/96
/144
/192
/240
/96
/120
F
(f
XX
t
/m)
F
2
C BUS
XX
m/2 × T
= 64 MHz, m = 192, t
Settable Internal System Clock
32.00 MHz to 33.52 MHz
32.00 MHz to 41.90 MHz
32.00 MHz to 33.52 MHz
32.00 MHz to 50.28 MHz
33.52 MHz to 64.00 MHz
41.90 MHz to 64.00 MHz
32.00 MHz to 33.52 MHz
32.00 MHz to 50.28 MHz
32.00 MHz to 64.00 MHz
40.00 MHz to 64.00 MHz
32.00 MHz to 33.52 MHz
40.00 MHz to 41.90 MHz
Frequency (f
SCL inversion
XX
) Range
R
= 200 ns, and t
Normal mode
(SMC0 bit = 0)
High-speed mode
(SMC0 bit = 1)
High-speed mode
(SMC0 bit = 1)
Operation Mode
F
= 50 ns is
871