UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 779

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(3) Transmission interrupt request signal
(a) Transmission enable interrupt request signal (INTUBTIT)
(b) FIFO transmission end interrupt request signal (INTUBTIF)
If the data to be transmitted next has not been written to the transmit data register, the transmit operation is
suspended.
Caution In the single mode, the transmission enable interrupt request signal (INTUBTIT) occurs
• In single mode (UBFIC0.UBMOD bit = 0)
• In FIFO mode (UBFIC0.UBMOD bit = 1)
• If pending mode is specified (UBFIC0.UBITM bit = 0) in FIFO mode
• If pointer mode is specified (UBFIC0.UBITM bit = 1) in FIFO mode
The FIFO transmission end interrupt request signal (INTUBTIF) occurs when no more data is in transmit
FIFO and the transmit shift register in the FIFO mode (UBFIC0.UBMOD bit = 1). After the INTUBTIF
signal has occurred, clear the pending INTUBTIT signal in the pending mode (UBFIC0.UBITM bit = 0) by
clearing the FIFO (UBFIC0.UBTFC bit = 1). If the INTUBTIF signal occurs because writing the next
transmit data to transmit FIFO is delayed (if all transmit data have not been transmitted), do not clear the
FIFO.
In the single mode, the transmission enable interrupt request signal (INTUBTIT) occurs when transmit
data can be written to the UBTX register (when 1 byte of data is transferred from the UBTX register to
the transmit shift register).
In the FIFO mode, the INTUBTIT signal occurs when transmit data of the number set as the trigger
specified by the UBFIC2.UBTT3 to UBFIC2.UBTT0 bits is transferred from transmit FIFO to the
transmit shift register (if transmit data of the number set as the trigger can be written).
If the pending mode is specified in the FIFO mode, the second INTUBTIT signal is held pending after
the first INTUBTIT signal has occurred, until as many transmit data as the number set as the trigger by
the UBFIC2.UBTT3 to UBFIC2.UBTT0 bits are written to transmit FIFO, even if the generation condition
of the second INTUBTIT signal is satisfied. When as many transmit data as the number set as the
trigger are written to transmit FIFO in response to the first INTUBTIT signal, the second pending
INTUBTIT signal is generated.
If the pointer mode is specified in the FIFO mode, the second INTUBTIT signal occurs when the
generation condition of the second INTUBTIT signal is satisfied even if as many transmit data as the
number set as the trigger by the UBFIC2.UBTT3 to UBFIC2.UBTT0 bits are not written to transmit FIFO
when the first INTUBTIT signal occurs.
when the UBTX register becomes empty (when 1 byte of data is transferred from the UBTX
register to the transmit shift register).
interrupt request signal (INTUBTIF) occurs when data is no longer in transmit FIFO and the
transmit shift register (when the FIFO and register are empty). However, the INTUBTIT
signal or INTUBTIF signal is not generated if the transmit data register becomes empty due
to RESET input.
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE B (UARTB)
User’s Manual U18279EJ3V0UD
In the FIFO mode, the FIFO transmission end
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