UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 965

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.3.2 DMA destination address registers 0 to 3 (DDA0 to DDA3)
They are divided into two 16-bit registers, DDAnH and DDAnL.
register, a new transfer destination address for DMA transfer can be specified during DMA transfer (see 19.8 Next
Address Setting Function). When setting the next address, the newly set value of the DDAn register is transferred
to the slave register and becomes valid only when DMA transfer has been completed normally and the DCHCn.TCn
bit is set to 1, or when the DCHCn.INITn bit is set to 1 (n = 0 to 3). However, the set value of the DDAn register is
invalid even when the DCHCn.Enn bit is cleared to 0 to disable DMA transfer and then the DDAn register is set.
The DDA0 to DDA3 registers set the DMA transfer destination address (28 bits) for DMA channel n (n = 0 to 3).
Since these registers are configured as 2-stage FIFO buffer registers consisting of the master register and slave
(1) DMA destination address registers 0H to 3H (DDA0H to DDA3H)
The DDA0H to DDA3H registers can be read or written in 16-bit units.
Reset makes these registers undefined.
Cautions 1. When setting an address of an on-chip peripheral I/O register for the destination address,
Caution Be sure to set bits 14 to 12 to “0”. If they are set to “1”, the operation is not guaranteed.
(n = 0 to 3)
DDAnH
2. Do not set the DDAnH register while DMA is suspended.
After reset:
be sure to specify an address between FFFF000H and FFFFFFFH. An address of the on-
chip peripheral I/O register image (3FFF000H to 3FFFFFFH) must not be specified.
DAn27 to
DAn16
DAn23
Undefined
IRAn
IRAn
15
0
1
7
CHAPTER 19 DMA FUNCTIONS (DMA CONTROLLER)
On-chip peripheral I/O
Internal RAM
Set the DMA transfer destination address (A27 to A16). During DMA
transfer, these bits store the next DMA transfer destination address.
DAn22
14
0
6
R/W
User’s Manual U18279EJ3V0UD
DAn21
Address: DDA0H FFFFF086H, DDA1H FFFFF08EH,
13
0
5
DMA transfer destination specification
DAn20
12
DDA2H FFFFF096H, DDA3H FFFFF09EH
0
4
DAn27
DAn19
11
3
DAn26
DAn18
10
2
DAn25
DAn17
9
1
DAn24
DAn16
8
0
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