UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 266

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

a PWM waveform from the TOAm1 pin.
newly written value is reflected when the count value of the 16-bit counter matches the value of the CCR0 buffer
register and the 16-bit counter is cleared to 0000H.
after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The
compare match interrupt request signal INTTAmCC1 is generated when the count value of the 16-bit counter matches
the value of the CCR1 buffer register.
bit counter matches the value of the CCRa buffer register and the 16-bit counter is cleared to 0000H.
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When the TAAmCE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
The PWM waveform can be changed by rewriting the TAAmCCRa register while the counter is operating. The
The compare match interrupt request signal INTTAmCC0 is generated when the 16-bit counter counts next time
The value set to the TAAmCCRa register is transferred to the CCRa buffer register when the count value of the 16-
Remark
Active level width = (Set value of TAAmCCR1 register) × Count clock cycle
Cycle = (Set value of TAAmCCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TAAmCCR1 register)/(Set value of TAAmCCR0 register + 1)
TAAmCCR0 register
CCR0 buffer register
TAAmCCR1 register
CCR1 buffer register
INTTAmCC0 signal
INTTAmCC1 signal
V850E/IF3: m = 2, 4, a = 0, 1
V850E/IG3: m = 2 to 4, a = 0, 1
TOAm0 pin output
TOAm1 pin output
16-bit counter
TAAmCE bit
FFFFH
0000H
CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA)
Figure 6-33. Basic Timing in PWM Output Mode
Active period
(D
D
10
10
D
)
User’s Manual U18279EJ3V0UD
00
D
D
(D
00
10
D
D
Cycle
D
00
10
10
D
00
+ 1)
00
D
Inactive period
(D
10
D
00
00
- D
10
+ 1)
D
D
11
01
D
01
D
D
D
D
11
11
01
11
D
01