UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 172

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

170
(2) Digital noise elimination 1 control register n (TANFCn)
Note V850E/IG3 only
The TANFCn register is used to select the sampling clock that is used to eliminate digital noise on the TIAn0 or
TIAn1 pin. If the same level is not detected on these pins three times in sequence using the clock selected by
the TANFCn register, the signal is eliminated as noise.
This register can be read or written in 8-bit units.
Reset sets this register to 00H.
Cautions 1. If the input signal lasts for the duration of 2 or 3 clocks, it is undefined whether the signal
V850E/IG3
V850E/IF3
n = 2 to 4
TANFCn
n = 2, 4
2. If noise is generated in synchronization with the sampling clock, eliminate the noise by
3. Noise is not eliminated if the pin is used as a normal input port pin.
4. The noise elimination function starts operating when the TAAnCTL0.TAAnCE bit is set to
After reset: 00H
is detected as a valid edge or eliminated as noise. So that the signal is actually detected
as a valid edge, the same signal level must be input for a duration of 3 clocks or more.
attaching a filter to the input pin.
1 (enabling count operations).
TANFENn
TANFENn
TANFCn0
0
1
0
1
7
Disables digital noise elimination
Enables digital noise elimination
f
f
XX
XX
R/W
/4
6
0
CHAPTER 4 PORT FUNCTIONS
User’s Manual U18279EJ3V0UD
Address: TANFC2 FFFFFB40H, TANFC3 FFFFFB42H
5
0
TANFC4 FFFFFB44H
Setting of digital noise elimination
Sampling clock selection
4
0
3
0
2
0
1
0
TANFCn0
Note
,
0