UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 757

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) UARTB status register (UBSTR)
The UBSTR register indicates the transfer status and reception error contents while UARTB is transmitting
data.
The status flag that indicates the transfer status during transmission indicates the data retention status of the
transmit shift register and transmit data register (the UBTX register in the single mode or transmit FIFO in the
FIFO mode). The status flag that indicates a reception error holds its status until it is cleared to 0.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
Caution When the UBCTL0.UBPWR bit or UBCTL0.UBRXE bit is set to 0, or when 0 is written to the
UBSTR
After reset: 00H
UBSTR register, the UBSTR.UBOVF, UBSTR.UBPE, UBSTR.UBFE, and UBSTR.UBOVE bits
are cleared to 0.
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE B (UARTB)
The value of the UBTSF bit is reflected after two periods of f
the transmit data is written to the UBTX register. Therefore, exercise care when
referencing the UBTSF bit after transmit data has been written to the UBTX register.
•
•
UBOVF
UBTSF
UBTSF
<7>
The UBOVF bit is valid only in the FIFO mode (when UBFIC0.UBMOD bit = 1),
and invalid in the single mode (when UBFIC0.UBMOD bit = 0).
If an overflow occurs, the received data is not written to receive FIFO but
discarded.
0
1
0
1
•
•
•
•
Overflow did not occur.
Overflow occurred (during reception).
R/W
Data to be transferred to the transmit shift register and transmit FIFO
does not exist (cleared (0) when UBCTL0.UBPWR bit = 0 or
UBCTL0.UBTXE bit = 0).
Data to be transferred to the transmit shift register or UBTX register
exists (transmission in progress).
Data to be transferred to the transmit shift register and transmit FIFO
exists (transmission in progress).
In single mode (UBFIC0.UBMOD bit = 0)
Data to be transferred to the transmit shift register and UBTX register
does not exist (cleared (0) when UBCTL0.UBPWR bit = 0 or
UBCTL0.UBTXE bit = 0).
In FIFO mode (UBFIC0.UBMOD bit = 1)
In single mode (UBFIC0.UBMOD bit = 0)
In FIFO mode (UBFIC0.UBMOD bit = 1)
6
0
Address: FFFFFA44H
User’s Manual U18279EJ3V0UD
5
0
4
0
Transfer status flag
Overflow flag
UBOVF
3
UBPE
<2>
XX
have elapsed, after
UBFE
<1>
UBOVE
<0>
(1/2)
755